
signal_response_issued
signal_response_issuedPrototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
voidReturns:
Notifies the testbench that a response has been driven out on the Avalon bus.Description:
Verilog HDLLanguage support:
Avalon-MM Slave BFM
Altera Corporation
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signal_response_issued
6-24
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