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Avalon-MM Verilog HDL and VHDL Testbenches

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Altera provides the Avalon-MM example testbench for both Verilog HDL and VHDL.

There are two versions of the Avalon-MM testbench. The first version tests a single Avalon-MM Master and

Slave pair. The second version includes two Avalon-MM Masters. Each Avalon-MM Master connects to

two Avalon-MM Slaves.

All of the testbench examples are included in ug_avalon_verification.zip. This file is available on the Altera

website as www.altera.com/literature/ug/ug_avalon_verification.zip.

Avalon-MM Verilog HDL Testbench Description

At the top-level, the Verilog HDL version of the Avalon-MM testbench includes two modules:

• The System Under Test- This module includes the Avalon-MM Master and Slaves components, the

Avalon-MM Master and Slave BFMs, and the Interconnect.

• The Test Program- The module includes Master Command, Master Response, and Slave Threads.

Figure 17-1: Verilog HDL Testbench for Two Avalon-MM Masters and Slaves

Interconnect

Avalon-MM

Master BFM

Avalon-MM

Master BFM

Avalon-MM

Slave BFM

Avalon-MM

Slave BFM

System Under Test

Master

Command

Thread

Test Program

Master

Response

Thread

Slave

Thread

The Master Command Thread performs the following functions:

• Generates random commands

• Passes the commands to Avalon-MM Master BFM

• Saves the commands in a FIFO for command and response verification

ISO

9001:2008

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