Altera Avalon Verification IP Suite Manual do Utilizador Página 59

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event_max_response_queue_size()
event_max_response_queue_size()Prototype:
Verilog HDL: N.A.
VHDL: bfm_id
Arguments:
voidReturns:
Notifies the testbench that the response queue size has reached the threshold limit.Description:
VHDLLanguage support:
event_min_response_queue_size()
event_min_response_queue_size()Prototype:
Verilog HDL: N.A.
VHDL: bfm_id
Arguments:
voidReturns:
Notifies the testbench that the response queue size is below the minimum limit.Description:
VHDLLanguage support:
get_clken()
logic get_clken()Prototype:
Verilog HDL: None
VHDL: clken, bfm_id, req_if(bfm_id)
Arguments:
logicReturns:
Returns the clock enable signal status.Description:
Verilog HDL, VHDLLanguage support:
get_command_address()
bit [AV_ADDRESS_W-1:0] get_command_address()Prototype:
Verilog HDL: None
VHDL: command_address, bfm_id, req_if(bfm_id)
Arguments:
bit [AV_ADDRESS_W-1:0]Returns:
Queries the received command descriptor for the transaction address.Description:
Verilog HDL, VHDLLanguage support:
Altera Corporation
Avalon-MM Slave BFM
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6-11
event_max_response_queue_size()
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