Altera IP Compiler for PCI Express Manual do Utilizador

101 Innovation DriveSan Jose, CA 95134www.altera.com UG-PCI10605-2014.08.18 User GuideIP Compiler for PCI ExpressDocument publication date:August 2014

1–8 Chapter 1: DatasheetGeneral DescriptionIP Compiler for PCI Express User Guide August 2014 Altera CorporationFigure 1–3 illustrates a heterogeneous

5–14 Chapter 5: IP Core InterfacesAvalon-ST InterfaceIP Compiler for PCI Express User Guide August 2014 Altera CorporationFigure 5–14 illustrates the

Chapter 5: IP Core Interfaces 5–15Avalon-ST InterfaceAugust 2014 Altera Corporation IP Compiler for PCI Express User Guide64- or 128-Bit Avalon-ST TX

5–16 Chapter 5: IP Core InterfacesAvalon-ST InterfaceIP Compiler for PCI Express User Guide August 2014 Altera Corporationtx_st_sop<n>1Istart of

Chapter 5: IP Core Interfaces 5–17Avalon-ST InterfaceAugust 2014 Altera Corporation IP Compiler for PCI Express User Guidetx_cred<n> (3) (4) (5)

5–18 Chapter 5: IP Core InterfacesAvalon-ST InterfaceIP Compiler for PCI Express User Guide August 2014 Altera CorporationFigure 5–16 illustrates the

Chapter 5: IP Core Interfaces 5–19Avalon-ST InterfaceAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideFigure 5–18 illustrates the

5–20 Chapter 5: IP Core InterfacesAvalon-ST InterfaceIP Compiler for PCI Express User Guide August 2014 Altera CorporationFigure 5–21 shows the mappin

Chapter 5: IP Core Interfaces 5–21Avalon-ST InterfaceAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideFigure 5–24 illustrates the

5–22 Chapter 5: IP Core InterfacesAvalon-ST InterfaceIP Compiler for PCI Express User Guide August 2014 Altera CorporationFigure 5–26 illustrates the

Chapter 5: IP Core Interfaces 5–23Avalon-ST InterfaceAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideClock Signals—Hard IP Implem

Chapter 1: Datasheet 1–9IP Core VerificationAugust 2014 Altera Corporation IP Compiler for PCI Express1 The device names and part numbers for Altera F

5–24 Chapter 5: IP Core InterfacesAvalon-ST InterfaceIP Compiler for PCI Express User Guide August 2014 Altera CorporationReset and Link Training Sign

Chapter 5: IP Core Interfaces 5–25Avalon-ST InterfaceAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideReset Details The hard IP im

5–26 Chapter 5: IP Core InterfacesAvalon-ST InterfaceIP Compiler for PCI Express User Guide August 2014 Altera CorporationFigure 5–27 provides a simpl

Chapter 5: IP Core Interfaces 5–27Avalon-ST InterfaceAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideECC Error SignalsTable 5–8 s

5–28 Chapter 5: IP Core InterfacesAvalon-ST InterfaceIP Compiler for PCI Express User Guide August 2014 Altera CorporationTable 5–10 shows the layout

Chapter 5: IP Core Interfaces 5–29Avalon-ST InterfaceAugust 2014 Altera Corporation IP Compiler for PCI Express User GuidePCI Express Interrupts for R

5–30 Chapter 5: IP Core InterfacesAvalon-ST InterfaceIP Compiler for PCI Express User Guide August 2014 Altera CorporationThe configuration space sign

Chapter 5: IP Core Interfaces 5–31Avalon-ST InterfaceAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideConfiguration Space Register

5–32 Chapter 5: IP Core InterfacesAvalon-ST InterfaceIP Compiler for PCI Express User Guide August 2014 Altera CorporationFigure 5–29 illustrates the

Chapter 5: IP Core Interfaces 5–33Avalon-ST InterfaceAugust 2014 Altera Corporation IP Compiler for PCI Express User Guideand global routing resources

1–10 Chapter 1: DatasheetPerformance and Resource UtilizationIP Compiler for PCI Express User Guide August 2014 Altera CorporationSimulation Environme

5–34 Chapter 5: IP Core InterfacesAvalon-ST InterfaceIP Compiler for PCI Express User Guide August 2014 Altera CorporationTable 5–15 describes the con

Chapter 5: IP Core Interfaces 5–35Avalon-ST InterfaceAugust 2014 Altera Corporation IP Compiler for PCI Express User Guidecfg_secbus8 O Secondary bus

5–36 Chapter 5: IP Core InterfacesAvalon-ST InterfaceIP Compiler for PCI Express User Guide August 2014 Altera CorporationConfiguration Space Signals—

Chapter 5: IP Core Interfaces 5–37Avalon-ST InterfaceAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideLMI Signals—Hard IP Implemen

5–38 Chapter 5: IP Core InterfacesAvalon-ST InterfaceIP Compiler for PCI Express User Guide August 2014 Altera CorporationLMI Read OperationFigure 5–3

Chapter 5: IP Core Interfaces 5–39Avalon-ST InterfaceAugust 2014 Altera Corporation IP Compiler for PCI Express User Guidef For a detailed description

5–40 Chapter 5: IP Core InterfacesAvalon-ST InterfaceIP Compiler for PCI Express User Guide August 2014 Altera CorporationTable 5–20 outlines the use

Chapter 5: IP Core Interfaces 5–41Avalon-ST InterfaceAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideFigure 5–35 illustrates the

5–42 Chapter 5: IP Core InterfacesAvalon-ST InterfaceIP Compiler for PCI Express User Guide August 2014 Altera Corporationf For a description of the c

Chapter 5: IP Core Interfaces 5–43Avalon-MM Application InterfaceAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideAvalon-MM Applic

Chapter 1: Datasheet 1–11Recommended Speed GradesAugust 2014 Altera Corporation IP Compiler for PCI Expressf Refer to Appendix C, Performance and Reso

5–44 Chapter 5: IP Core InterfacesAvalon-MM Application InterfaceIP Compiler for PCI Express User Guide August 2014 Altera CorporationFigure 5–36 show

Chapter 5: IP Core Interfaces 5–45Avalon-MM Application InterfaceAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideFigure 5–37 show

5–46 Chapter 5: IP Core InterfacesAvalon-MM Application InterfaceIP Compiler for PCI Express User Guide August 2014 Altera CorporationFigure 5–38 show

Chapter 5: IP Core Interfaces 5–47Avalon-MM Application InterfaceAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideFigure 5–39 show

5–48 Chapter 5: IP Core InterfacesAvalon-MM Application InterfaceIP Compiler for PCI Express User Guide August 2014 Altera Corporationf The IP Compile

Chapter 5: IP Core Interfaces 5–49Avalon-MM Application InterfaceAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideRX Avalon-MM Mas

5–50 Chapter 5: IP Core InterfacesAvalon-MM Application InterfaceIP Compiler for PCI Express User Guide August 2014 Altera Corporation64-Bit Bursting

Chapter 5: IP Core Interfaces 5–51Avalon-MM Application InterfaceAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideClock SignalsTab

5–52 Chapter 5: IP Core InterfacesAvalon-MM Application InterfaceIP Compiler for PCI Express User Guide August 2014 Altera CorporationFigure 5–40 show

Chapter 5: IP Core Interfaces 5–53Physical Layer Interface SignalsAugust 2014 Altera Corporation IP Compiler for PCI Express User GuidePhysical Layer

1–12 Chapter 1: DatasheetRecommended Speed GradesIP Compiler for PCI Express User Guide August 2014 Altera Corporationf Refer to “Setting Up and Runni

5–54 Chapter 5: IP Core InterfacesPhysical Layer Interface SignalsIP Compiler for PCI Express User Guide August 2014 Altera CorporationAn offset_cance

Chapter 5: IP Core Interfaces 5–55Physical Layer Interface SignalsAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideSerial Interfac

5–56 Chapter 5: IP Core InterfacesPhysical Layer Interface SignalsIP Compiler for PCI Express User Guide August 2014 Altera Corporationassigned in ord

Chapter 5: IP Core Interfaces 5–57Physical Layer Interface SignalsAugust 2014 Altera Corporation IP Compiler for PCI Express User Guidefor simulation

5–58 Chapter 5: IP Core InterfacesTest SignalsIP Compiler for PCI Express User Guide August 2014 Altera CorporationTest SignalsThe test_in and test_ou

Chapter 5: IP Core Interfaces 5–59Test SignalsAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideTest Interface Signals—Hard IP Impl

5–60 Chapter 5: IP Core InterfacesTest SignalsIP Compiler for PCI Express User Guide August 2014 Altera CorporationThe test_out bus allows you to moni

Chapter 5: IP Core Interfaces 5–61Test SignalsAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideTest Interface Signals—Soft IP Impl

5–62 Chapter 5: IP Core InterfacesTest SignalsIP Compiler for PCI Express User Guide August 2014 Altera CorporationAvalon-ST Test SignalsThe Avalon-ST

August 2014 Altera Corporation IP Compiler for PCI Express User Guide6. Register DescriptionsThis chapter describes registers that you can access in t

Chapter 1: Datasheet 1–13Recommended Speed GradesAugust 2014 Altera Corporation IP Compiler for PCI ExpressStratix IV GX Gen1 ×1 62.5 all speed grades

6–2 Chapter 6: Register DescriptionsConfiguration Space Register ContentIP Compiler for PCI Express User Guide August 2014 Altera CorporationTable 6–2

Chapter 6: Register Descriptions 6–3Configuration Space Register ContentAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideTable 6–3

6–4 Chapter 6: Register DescriptionsConfiguration Space Register ContentIP Compiler for PCI Express User Guide August 2014 Altera CorporationTable 6–5

Chapter 6: Register Descriptions 6–5Configuration Space Register ContentAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideTable 6–8

6–6 Chapter 6: Register DescriptionsPCI Express Avalon-MM Bridge Control Register ContentIP Compiler for PCI Express User Guide August 2014 Altera Cor

Chapter 6: Register Descriptions 6–7PCI Express Avalon-MM Bridge Control Register ContentAugust 2014 Altera Corporation IP Compiler for PCI Express Us

6–8 Chapter 6: Register DescriptionsPCI Express Avalon-MM Bridge Control Register ContentIP Compiler for PCI Express User Guide August 2014 Altera Cor

Chapter 6: Register Descriptions 6–9PCI Express Avalon-MM Bridge Control Register ContentAugust 2014 Altera Corporation IP Compiler for PCI Express Us

6–10 Chapter 6: Register DescriptionsPCI Express Avalon-MM Bridge Control Register ContentIP Compiler for PCI Express User Guide August 2014 Altera Co

Chapter 6: Register Descriptions 6–11PCI Express Avalon-MM Bridge Control Register ContentAugust 2014 Altera Corporation IP Compiler for PCI Express U

1–14 Chapter 1: DatasheetRecommended Speed GradesIP Compiler for PCI Express User Guide August 2014 Altera Corporation

6–12 Chapter 6: Register DescriptionsComprehensive Correspondence between Config Space Registers and PCIe Spec Rev 2.0IP Compiler for PCI Express User

Chapter 6: Register Descriptions 6–13Comprehensive Correspondence between Config Space Registers and PCIe Spec Rev 2.0August 2014 Altera Corporation I

6–14 Chapter 6: Register DescriptionsComprehensive Correspondence between Config Space Registers and PCIe Spec Rev 2.0IP Compiler for PCI Express User

Chapter 6: Register Descriptions 6–15Comprehensive Correspondence between Config Space Registers and PCIe Spec Rev 2.0August 2014 Altera Corporation I

6–16 Chapter 6: Register DescriptionsComprehensive Correspondence between Config Space Registers and PCIe Spec Rev 2.0IP Compiler for PCI Express User

August 2014 Altera Corporation IP Compiler for PCI Express User Guide7. Reset and ClocksThis chapter covers the functional aspects of the reset and cl

7–2 Chapter 7: Reset and ClocksReset Hard IP ImplementationIP Compiler for PCI Express User Guide August 2014 Altera Corporation test_in settingsFigur

Chapter 7: Reset and Clocks 7–3Reset Hard IP ImplementationAugust 2014 Altera Corporation IP Compiler for PCI Express User Guideqmegawiz -silent -wiz_

7–4 Chapter 7: Reset and ClocksReset Soft IP ImplementationIP Compiler for PCI Express User Guide August 2014 Altera CorporationReset Soft IP Implemen

Chapter 7: Reset and Clocks 7–5ClocksAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideClocksThis section describes clocking for th

August 2014 Altera Corporation IP Compiler for PCI Express User Guide2. Getting StartedThis section provides step-by-step instructions to help you qui

7–6 Chapter 7: Reset and ClocksClocksIP Compiler for PCI Express User Guide August 2014 Altera CorporationThe IP core contains a clock domain crossing

Chapter 7: Reset and Clocks 7–7ClocksAugust 2014 Altera Corporation IP Compiler for PCI Express User Guidecore_clk, core_clk_outThe core_clk signal is

7–8 Chapter 7: Reset and ClocksClocksIP Compiler for PCI Express User Guide August 2014 Altera CorporationThe input clocks are used for the following

Chapter 7: Reset and Clocks 7–9ClocksAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideRefer to Figure 7–6 for this clocking config

7–10 Chapter 7: Reset and ClocksClocksIP Compiler for PCI Express User Guide August 2014 Altera CorporationRefer to Figure 7–7 for this clocking confi

Chapter 7: Reset and Clocks 7–11ClocksAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideClocking for a Generic PIPE PHY and the Sim

7–12 Chapter 7: Reset and ClocksClocksIP Compiler for PCI Express User Guide August 2014 Altera Corporation

August 2014 Altera Corporation IP Compiler for PCI Express User Guide8. Transaction Layer Protocol (TLP)DetailsThis chapter provides detailed informat

8–2 Chapter 8: Transaction Layer Protocol (TLP) DetailsSupported Message TypesIP Compiler for PCI Express User Guide August 2014 Altera CorporationErr

Chapter 8: Transaction Layer Protocol (TLP) Details 8–3Transaction Layer Routing RulesAugust 2014 Altera Corporation IP Compiler for PCI Express User

2–2 Chapter 2: Getting StartedIP Catalog and Parameter EditorIP Compiler for PCI Express User Guide August 2014 Altera Corporation Tethered—run the d

8–4 Chapter 8: Transaction Layer Protocol (TLP) DetailsReceive Buffer ReorderingIP Compiler for PCI Express User Guide August 2014 Altera Corporation

Chapter 8: Transaction Layer Protocol (TLP) Details 8–5Receive Buffer ReorderingAugust 2014 Altera Corporation IP Compiler for PCI Express User Guide1

8–6 Chapter 8: Transaction Layer Protocol (TLP) DetailsReceive Buffer ReorderingIP Compiler for PCI Express User Guide August 2014 Altera Corporation

August 2014 Altera Corporation IP Compiler for PCI Express User Guide9. Optional FeaturesThis chapter provides information on several addition topics.

9–2 Chapter 9: Optional FeaturesECRCIP Compiler for PCI Express User Guide August 2014 Altera CorporationTable 9–1 summarizes the RX ECRC functionalit

Chapter 9: Optional Features 9–3Active State Power Management (ASPM)August 2014 Altera Corporation IP Compiler for PCI Express User GuideActive State

9–4 Chapter 9: Optional FeaturesActive State Power Management (ASPM)IP Compiler for PCI Express User Guide August 2014 Altera CorporationExit LatencyA

Chapter 9: Optional Features 9–5Lane Initialization and ReversalAugust 2014 Altera Corporation IP Compiler for PCI Express User Guide For L0s, the co

9–6 Chapter 9: Optional FeaturesInstantiating Multiple IP Compiler for PCI Express InstancesIP Compiler for PCI Express User Guide August 2014 Altera

Chapter 9: Optional Features 9–7Instantiating Multiple IP Compiler for PCI Express InstancesAugust 2014 Altera Corporation IP Compiler for PCI Express

Chapter 2: Getting Started 2–3IP Catalog and Parameter EditorAugust 2014 Altera Corporation IP Compiler for PCI Express User Guide Right-click an IP

9–8 Chapter 9: Optional FeaturesInstantiating Multiple IP Compiler for PCI Express InstancesIP Compiler for PCI Express User Guide August 2014 Altera

August 2014 Altera Corporation IP Compiler for PCI Express User Guide10. InterruptsThis chapter covers interrupts for endpoints and root ports. PCI Ex

10–2 Chapter 10: InterruptsMSI InterruptsIP Compiler for PCI Express User Guide August 2014 Altera CorporationFigure 10–2 illustrates a possible imple

Chapter 10: Interrupts 10–3MSI-XAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideFigure 10–4 illustrates the interactions among MS

10–4 Chapter 10: InterruptsPCI Express Interrupts for Root PortsIP Compiler for PCI Express User Guide August 2014 Altera CorporationFigure 10–5 illus

Chapter 10: Interrupts 10–5PCI Express Interrupts for Root PortsAugust 2014 Altera Corporation IP Compiler for PCI Express User Guide When the AER op

10–6 Chapter 10: InterruptsPCI Express Interrupts for Root PortsIP Compiler for PCI Express User Guide August 2014 Altera Corporation

August 2014 Altera Corporation IP Compiler for PCI Express User Guide11. Flow ControlThroughput analysis requires that you understand the Flow Control

11–2 Chapter 11: Flow ControlThroughput of Posted WritesIP Compiler for PCI Express User Guide August 2014 Altera CorporationEach receiver also mainta

Chapter 11: Flow Control 11–3Throughput of Posted WritesAugust 2014 Altera Corporation IP Compiler for PCI Express User Guide6. After an FC Update DLL

IP Compiler for PCI Express User Guide August 2014 Altera Corporation© 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY,

2–4 Chapter 2: Getting StartedUpgrading Outdated IP CoresIP Compiler for PCI Express User Guide August 2014 Altera Corporation Generate testbench sys

11–4 Chapter 11: Flow ControlThroughput of Non-Posted ReadsIP Compiler for PCI Express User Guide August 2014 Altera CorporationBased on the above FC

Chapter 11: Flow Control 11–5Throughput of Non-Posted ReadsAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideNevertheless, maintain

11–6 Chapter 11: Flow ControlThroughput of Non-Posted ReadsIP Compiler for PCI Express User Guide August 2014 Altera CorporationYou can also control t

August 2014 Altera Corporation IP Compiler for PCI Express User Guide12. Error HandlingEach PCI Express compliant device must implement a basic level

12–2 Chapter 12: Error HandlingPhysical Layer ErrorsIP Compiler for PCI Express User Guide August 2014 Altera CorporationPhysical Layer ErrorsTable 12

Chapter 12: Error Handling 12–3Transaction Layer ErrorsAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideTransaction Layer ErrorsTa

12–4 Chapter 12: Error HandlingTransaction Layer ErrorsIP Compiler for PCI Express User Guide August 2014 Altera CorporationUnsupported requests for r

Chapter 12: Error Handling 12–5Error Reporting and Data PoisoningAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideError Reporting

12–6 Chapter 12: Error HandlingUncorrectable and Correctable Error Status BitsIP Compiler for PCI Express User Guide August 2014 Altera CorporationPoi

Chapter 12: Error Handling 12–7Uncorrectable and Correctable Error Status BitsAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideFig

Chapter 2: Getting Started 2–5Upgrading Outdated IP CoresAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideThe upgrade process rena

12–8 Chapter 12: Error HandlingUncorrectable and Correctable Error Status BitsIP Compiler for PCI Express User Guide August 2014 Altera Corporation

August 2014 Altera Corporation IP Compiler for PCI Express User Guide13. Reconfiguration and OffsetCancellationThis chapter describes features of the

13–2 Chapter 13: Reconfiguration and Offset CancellationDynamic ReconfigurationIP Compiler for PCI Express User Guide August 2014 Altera CorporationTa

Chapter 13: Reconfiguration and Offset Cancellation 13–3Dynamic ReconfigurationAugust 2014 Altera Corporation IP Compiler for PCI Express User Guide3S

13–4 Chapter 13: Reconfiguration and Offset CancellationDynamic ReconfigurationIP Compiler for PCI Express User Guide August 2014 Altera Corporation0x

Chapter 13: Reconfiguration and Offset Cancellation 13–5Dynamic ReconfigurationAugust 2014 Altera Corporation IP Compiler for PCI Express User Guide3:

13–6 Chapter 13: Reconfiguration and Offset CancellationDynamic ReconfigurationIP Compiler for PCI Express User Guide August 2014 Altera Corporation0x

Chapter 13: Reconfiguration and Offset Cancellation 13–7Dynamic ReconfigurationAugust 2014 Altera Corporation IP Compiler for PCI Express User Guide0x

13–8 Chapter 13: Reconfiguration and Offset CancellationDynamic ReconfigurationIP Compiler for PCI Express User Guide August 2014 Altera Corporation0x

Chapter 13: Reconfiguration and Offset Cancellation 13–9Transceiver Offset CancellationAugust 2014 Altera Corporation IP Compiler for PCI Express User

2–6 Chapter 2: Getting StartedUpgrading Outdated IP CoresIP Compiler for PCI Express User Guide August 2014 Altera Corporation2. To simultaneously upg

13–10 Chapter 13: Reconfiguration and Offset CancellationTransceiver Offset CancellationIP Compiler for PCI Express User Guide August 2014 Altera Corp

August 2014 Altera Corporation IP Compiler for PCI Express User Guide14. External PHYsExternal PHY SupportThis chapter discusses external PHY support,

14–2 Chapter 14: External PHYsExternal PHY SupportIP Compiler for PCI Express User Guide August 2014 Altera Corporation1 The refclk is the same as pcl

Chapter 14: External PHYs 14–3External PHY SupportAugust 2014 Altera Corporation IP Compiler for PCI Express User Guide refclk clocks a single data ra

14–4 Chapter 14: External PHYsExternal PHY SupportIP Compiler for PCI Express User Guide August 2014 Altera Corporationsource file referenced in your

Chapter 14: External PHYs 14–5External PHY SupportAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideAn edge detect circuit detects

14–6 Chapter 14: External PHYsExternal PHY SupportIP Compiler for PCI Express User Guide August 2014 Altera Corporation<path>/ip/ip_compiler_for

Chapter 14: External PHYs 14–7External PHY SupportAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideAn edge detect circuit detects

14–8 Chapter 14: External PHYsExternal PHY SupportIP Compiler for PCI Express User Guide August 2014 Altera Corporationpipe_txclkOSource synchronous t

Chapter 14: External PHYs 14–9External PHY SupportAugust 2014 Altera Corporation IP Compiler for PCI Express User Guide8-bit PHY Interface SignalsTabl

Chapter 2: Getting Started 2–7Parameterizing the IP Compiler for PCI ExpressAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideParam

14–10 Chapter 14: External PHYsSelecting an External PHYIP Compiler for PCI Express User Guide August 2014 Altera CorporationSelecting an External PHY

Chapter 14: External PHYs 14–11External PHY Constraint SupportAugust 2014 Altera Corporation IP Compiler for PCI Express User Guide Select the type o

14–12 Chapter 14: External PHYsExternal PHY Constraint SupportIP Compiler for PCI Express User Guide August 2014 Altera Corporation1 To meet timing fo

August 2014 Altera Corporation IP Compiler for PCI Express User Guide15. Testbench and Design ExampleThis chapter introduces the root port or endpoint

15–2 Chapter 15: Testbench and Design ExampleEndpoint TestbenchIP Compiler for PCI Express User Guide August 2014 Altera CorporationYour application l

Chapter 15: Testbench and Design Example 15–3Endpoint TestbenchAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideThis testbench sim

15–4 Chapter 15: Testbench and Design ExampleRoot Port TestbenchIP Compiler for PCI Express User Guide August 2014 Altera CorporationThe testbench has

Chapter 15: Testbench and Design Example 15–5Root Port TestbenchAugust 2014 Altera Corporation IP Compiler for PCI Express User Guide <variation n

15–6 Chapter 15: Testbench and Design ExampleChaining DMA Design ExampleIP Compiler for PCI Express User Guide August 2014 Altera CorporationThe testb

Chapter 15: Testbench and Design Example 15–7Chaining DMA Design ExampleAugust 2014 Altera Corporation IP Compiler for PCI Express User Guide1 The cha

2–8 Chapter 2: Getting StartedParameterizing the IP Compiler for PCI ExpressIP Compiler for PCI Express User Guide August 2014 Altera Corporation5. Sp

15–8 Chapter 15: Testbench and Design ExampleChaining DMA Design ExampleIP Compiler for PCI Express User Guide August 2014 Altera CorporationFigure 15

Chapter 15: Testbench and Design Example 15–9Chaining DMA Design ExampleAugust 2014 Altera Corporation IP Compiler for PCI Express User Guide The des

15–10 Chapter 15: Testbench and Design ExampleChaining DMA Design ExampleIP Compiler for PCI Express User Guide August 2014 Altera CorporationThe foll

Chapter 15: Testbench and Design Example 15–11Chaining DMA Design ExampleAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideThe foll

15–12 Chapter 15: Testbench and Design ExampleChaining DMA Design ExampleIP Compiler for PCI Express User Guide August 2014 Altera Corporationas well

Chapter 15: Testbench and Design Example 15–13Chaining DMA Design ExampleAugust 2014 Altera Corporation IP Compiler for PCI Express User Guide altpci

15–14 Chapter 15: Testbench and Design ExampleChaining DMA Design ExampleIP Compiler for PCI Express User Guide August 2014 Altera CorporationChaining

Chapter 15: Testbench and Design Example 15–15Chaining DMA Design ExampleAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideTable 15

15–16 Chapter 15: Testbench and Design ExampleChaining DMA Design ExampleIP Compiler for PCI Express User Guide August 2014 Altera CorporationTable 15

Chapter 15: Testbench and Design Example 15–17Chaining DMA Design ExampleAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideChaining

Chapter 2: Getting Started 2–9Parameterizing the IP Compiler for PCI ExpressAugust 2014 Altera Corporation IP Compiler for PCI Express User Guide6. Cl

15–18 Chapter 15: Testbench and Design ExampleTest Driver ModuleIP Compiler for PCI Express User Guide August 2014 Altera CorporationTable 15–11 shows

Chapter 15: Testbench and Design Example 15–19Test Driver ModuleAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideFor a root port V

15–20 Chapter 15: Testbench and Design ExampleTest Driver ModuleIP Compiler for PCI Express User Guide August 2014 Altera Corporation2. Sets up the ch

Chapter 15: Testbench and Design Example 15–21Test Driver ModuleAugust 2014 Altera Corporation IP Compiler for PCI Express User Guide3. Waits for the

15–22 Chapter 15: Testbench and Design ExampleRoot Port Design ExampleIP Compiler for PCI Express User Guide August 2014 Altera Corporation2. Sets up

Chapter 15: Testbench and Design Example 15–23Root Port Design ExampleAugust 2014 Altera Corporation IP Compiler for PCI Express User Guide Test Driv

15–24 Chapter 15: Testbench and Design ExampleRoot Port Design ExampleIP Compiler for PCI Express User Guide August 2014 Altera Corporation <varia

Chapter 15: Testbench and Design Example 15–25Root Port Design ExampleAugust 2014 Altera Corporation IP Compiler for PCI Express User Guide altpcierd

15–26 Chapter 15: Testbench and Design ExampleRoot Port BFMIP Compiler for PCI Express User Guide August 2014 Altera CorporationRoot Port BFMThe basic

Chapter 15: Testbench and Design Example 15–27Root Port BFMAugust 2014 Altera Corporation IP Compiler for PCI Express User Guide BFM Configuration Pr

2–10 Chapter 2: Getting StartedViewing the Generated FilesIP Compiler for PCI Express User Guide August 2014 Altera Corporation9. On the Summary tab,

15–28 Chapter 15: Testbench and Design ExampleRoot Port BFMIP Compiler for PCI Express User Guide August 2014 Altera CorporationBFM Memory Map The BFM

Chapter 15: Testbench and Design Example 15–29Root Port BFMAugust 2014 Altera Corporation IP Compiler for PCI Express User Guide3. Assigns values to a

15–30 Chapter 15: Testbench and Design ExampleRoot Port BFMIP Compiler for PCI Express User Guide August 2014 Altera CorporationThe ebfm_cfg_rp_ep pro

Chapter 15: Testbench and Design Example 15–31Root Port BFMAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideBesides the ebfm_cfg_r

15–32 Chapter 15: Testbench and Design ExampleRoot Port BFMIP Compiler for PCI Express User Guide August 2014 Altera CorporationIf addr_map_4GB_limit

Chapter 15: Testbench and Design Example 15–33Root Port BFMAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideFigure 15–9 shows the

15–34 Chapter 15: Testbench and Design ExampleBFM Procedures and FunctionsIP Compiler for PCI Express User Guide August 2014 Altera Corporation ebfm_b

Chapter 15: Testbench and Design Example 15–35BFM Procedures and FunctionsAugust 2014 Altera Corporation IP Compiler for PCI Express User Guideebfm_ba

15–36 Chapter 15: Testbench and Design ExampleBFM Procedures and FunctionsIP Compiler for PCI Express User Guide August 2014 Altera Corporationebfm_ba

Chapter 15: Testbench and Design Example 15–37BFM Procedures and FunctionsAugust 2014 Altera Corporation IP Compiler for PCI Express User Guideebfm_cf

Chapter 2: Getting Started 2–11Viewing the Generated FilesAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideFigure 2–6 illustrates

15–38 Chapter 15: Testbench and Design ExampleBFM Procedures and FunctionsIP Compiler for PCI Express User Guide August 2014 Altera Corporationebfm_cf

Chapter 15: Testbench and Design Example 15–39BFM Procedures and FunctionsAugust 2014 Altera Corporation IP Compiler for PCI Express User Guideebfm_cf

15–40 Chapter 15: Testbench and Design ExampleBFM Procedures and FunctionsIP Compiler for PCI Express User Guide August 2014 Altera Corporationebfm_cf

Chapter 15: Testbench and Design Example 15–41BFM Procedures and FunctionsAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideShared

15–42 Chapter 15: Testbench and Design ExampleBFM Procedures and FunctionsIP Compiler for PCI Express User Guide August 2014 Altera Corporationshmem_d

Chapter 15: Testbench and Design Example 15–43BFM Procedures and FunctionsAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideBFM Log

15–44 Chapter 15: Testbench and Design ExampleBFM Procedures and FunctionsIP Compiler for PCI Express User Guide August 2014 Altera CorporationAll of

Chapter 15: Testbench and Design Example 15–45BFM Procedures and FunctionsAugust 2014 Altera Corporation IP Compiler for PCI Express User Guide When

15–46 Chapter 15: Testbench and Design ExampleBFM Procedures and FunctionsIP Compiler for PCI Express User Guide August 2014 Altera Corporationebfm_lo

Chapter 15: Testbench and Design Example 15–47BFM Procedures and FunctionsAugust 2014 Altera Corporation IP Compiler for PCI Express User Guidehimage

2–12 Chapter 2: Getting StartedSimulating the DesignIP Compiler for PCI Express User Guide August 2014 Altera CorporationThe Stratix IV .zip file incl

15–48 Chapter 15: Testbench and Design ExampleBFM Procedures and FunctionsIP Compiler for PCI Express User Guide August 2014 Altera Corporationhimage2

Chapter 15: Testbench and Design Example 15–49BFM Procedures and FunctionsAugust 2014 Altera Corporation IP Compiler for PCI Express User Guidedimage1

15–50 Chapter 15: Testbench and Design ExampleBFM Procedures and FunctionsIP Compiler for PCI Express User Guide August 2014 Altera Corporationdimage4

Chapter 15: Testbench and Design Example 15–51BFM Procedures and FunctionsAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideProcedu

15–52 Chapter 15: Testbench and Design ExampleBFM Procedures and FunctionsIP Compiler for PCI Express User Guide August 2014 Altera Corporationdma_wr_

Chapter 15: Testbench and Design Example 15–53BFM Procedures and FunctionsAugust 2014 Altera Corporation IP Compiler for PCI Express User Guiderc_memp

15–54 Chapter 15: Testbench and Design ExampleBFM Procedures and FunctionsIP Compiler for PCI Express User Guide August 2014 Altera Corporationdma_set

Chapter 15: Testbench and Design Example 15–55BFM Procedures and FunctionsAugust 2014 Altera Corporation IP Compiler for PCI Express User Guidedma_set

15–56 Chapter 15: Testbench and Design ExampleBFM Procedures and FunctionsIP Compiler for PCI Express User Guide August 2014 Altera Corporation

August 2014 Altera Corporation IP Compiler for PCI Express User Guide16. Qsys Design ExampleThe Qsys design example provides detailed step-by-step ins

Chapter 2: Getting Started 2–13Simulating the DesignAugust 2014 Altera Corporation IP Compiler for PCI Express User Guide Root port to endpoint memor

16–2 Chapter 16: Qsys Design ExampleCreating a Quartus II ProjectIP Compiler for PCI Express User Guide August 2014 Altera CorporationFigure 16–1 show

Chapter 16: Qsys Design Example 16–3Running QsysAugust 2014 Altera Corporation IP Compiler for PCI Express User Guide2. On the Quartus II File menu, c

16–4 Chapter 16: Qsys Design ExampleParameterizing the IP Compiler for PCI ExpressIP Compiler for PCI Express User Guide August 2014 Altera Corporatio

Chapter 16: Qsys Design Example 16–5Parameterizing the IP Compiler for PCI ExpressAugust 2014 Altera Corporation IP Compiler for PCI Express User Guid

16–6 Chapter 16: Qsys Design ExampleAdding the Remaining Components to the Qsys SystemIP Compiler for PCI Express User Guide August 2014 Altera Corpor

Chapter 16: Qsys Design Example 16–7Completing the Connections in QsysAugust 2014 Altera Corporation IP Compiler for PCI Express User Guide3. Click Fi

16–8 Chapter 16: Qsys Design ExampleCompleting the Connections in QsysIP Compiler for PCI Express User Guide August 2014 Altera Corporation2. Connect

Chapter 16: Qsys Design Example 16–9Specifying Exported InterfacesAugust 2014 Altera Corporation IP Compiler for PCI Express User Guide4. In the IRQ p

16–10 Chapter 16: Qsys Design ExampleSpecifying Address AssignmentsIP Compiler for PCI Express User Guide August 2014 Altera CorporationSpecifying Add

Chapter 16: Qsys Design Example 16–11Specifying Address AssignmentsAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideFigure 16–3 sh

August 2014 Altera Corporation IP Compiler for PCI Express User Guide1. DatasheetThis document describes the Altera® IP Compiler for PCI Express IP co

2–14 Chapter 2: Getting StartedSimulating the DesignIP Compiler for PCI Express User Guide August 2014 Altera CorporationExample 2-1 continued## INFO:

16–12 Chapter 16: Qsys Design ExampleGenerating the Qsys SystemIP Compiler for PCI Express User Guide August 2014 Altera CorporationFigure 16–4 illust

Chapter 16: Qsys Design Example 16–13Simulating the Qsys SystemAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideTable 16–13 lists

16–14 Chapter 16: Qsys Design ExampleSimulating the Qsys SystemIP Compiler for PCI Express User Guide August 2014 Altera CorporationFigure 16–5 shows

Chapter 16: Qsys Design Example 16–15Simulating the Qsys SystemAugust 2014 Altera Corporation IP Compiler for PCI Express User Guide7. Open the file a

16–16 Chapter 16: Qsys Design ExampleSimulating the Qsys SystemIP Compiler for PCI Express User Guide August 2014 Altera Corporation6. To use a wavefo

Chapter 16: Qsys Design Example 16–17Preparing the Design for CompilationAugust 2014 Altera Corporation IP Compiler for PCI Express User GuidePreparin

16–18 Chapter 16: Qsys Design ExamplePreparing the Design for CompilationIP Compiler for PCI Express User Guide August 2014 Altera CorporationAdding F

Chapter 16: Qsys Design Example 16–19Compiling the DesignAugust 2014 Altera Corporation IP Compiler for PCI Express User Guide8. In the Settings windo

16–20 Chapter 16: Qsys Design ExampleProgramming a DeviceIP Compiler for PCI Express User Guide August 2014 Altera Corporation

August 2014 Altera Corporation IP Compiler for PCI Express User Guide17. DebuggingAs you bring up your PCI Express system, you may face a number of is

Chapter 2: Getting Started 2–15Simulating the DesignAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideExample 2-1 continued# INFO:

17–2 Chapter 17: DebuggingHardware Bring-Up IssuesIP Compiler for PCI Express User Guide August 2014 Altera CorporationCheck Link Training and Status

Chapter 17: Debugging 17–3Link and Transceiver TestingAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideIf you are using the soft I

17–4 Chapter 17: DebuggingLink and Transceiver TestingIP Compiler for PCI Express User Guide August 2014 Altera CorporationTo support data integrity w

August 2014 Altera Corporation IP Compiler for PCI Express User GuideA. Transaction Layer Packet (TLP) HeaderFormatsTLP Packet Format without Data Pay

A–2 Chapter :TLP Packet Format without Data PayloadIP Compiler for PCI Express User Guide August 2014 Altera Corporation\Byte 8Address[31:2]00Byte 12R

Chapter : A–3TLP Packet Format with Data PayloadAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideTLP Packet Format with Data Paylo

A–4 Chapter :TLP Packet Format with Data PayloadIP Compiler for PCI Express User Guide August 2014 Altera CorporationByte 0 011000000TC0000TD EPAttr00

Chapter : A–5TLP Packet Format with Data PayloadAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideTable A–17. Message with Data+0 +

A–6 Chapter :TLP Packet Format with Data PayloadIP Compiler for PCI Express User Guide August 2014 Altera Corporation

August 2014 Altera Corporation IP Compiler for PCI Express User GuideB. IP Compiler for PCI Express Core withthe Descriptor/Data InterfaceThis chapter

2–16 Chapter 2: Getting StartedConstraining the DesignIP Compiler for PCI Express User Guide August 2014 Altera CorporationConstraining the DesignThe

B–2 Chapter :Descriptor/Data InterfaceIP Compiler for PCI Express User Guide August 2014 Altera CorporationFigure B–2 shows all the signals for IP Com

Chapter : B–3Descriptor/Data InterfaceAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideIn Figure B–2, the transmit and receive sig

B–4 Chapter :Descriptor/Data InterfaceIP Compiler for PCI Express User Guide August 2014 Altera CorporationTable B–2 describes the standard RX descrip

Chapter : B–5Descriptor/Data InterfaceAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideThe IP core generates the eight MSBs of thi

B–6 Chapter :Descriptor/Data InterfaceIP Compiler for PCI Express User Guide August 2014 Altera CorporationTransaction Examples Using Receive Signals

Chapter : B–7Descriptor/Data InterfaceAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideTransaction without Data PayloadIn Figure B

B–8 Chapter :Descriptor/Data InterfaceIP Compiler for PCI Express User Guide August 2014 Altera CorporationEach virtual channel has a dedicated datapa

Chapter : B–9Descriptor/Data InterfaceAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideTransaction AbortedIn Figure B–7, a memory

B–10 Chapter :Descriptor/Data InterfaceIP Compiler for PCI Express User Guide August 2014 Altera CorporationNormally, rx_dfr is asserted on the same o

Chapter : B–11Descriptor/Data InterfaceAugust 2014 Altera Corporation IP Compiler for PCI Express User Guide The application layer deasserts rx_ws at

Chapter 2: Getting Started 2–17Constraining the DesignAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideExample 2–2 illustrates the

B–12 Chapter :Descriptor/Data InterfaceIP Compiler for PCI Express User Guide August 2014 Altera CorporationTransmit Operation Interface SignalsThe tr

Chapter : B–13Descriptor/Data InterfaceAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideTable B–7 describes the standard TX data p

B–14 Chapter :Descriptor/Data InterfaceIP Compiler for PCI Express User Guide August 2014 Altera Corporationtx_data<n>[63:0]ITransmit data bus.

Chapter : B–15Descriptor/Data InterfaceAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideTable B–8 describes the advanced data phas

B–16 Chapter :Descriptor/Data InterfaceIP Compiler for PCI Express User Guide August 2014 Altera CorporationTable B–10 shows the bit information for t

Chapter : B–17Descriptor/Data InterfaceAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideTransaction Examples Using Transmit Signal

B–18 Chapter :Descriptor/Data InterfaceIP Compiler for PCI Express User Guide August 2014 Altera CorporationFigure B–13 shows the IP core transmitting

Chapter : B–19Descriptor/Data InterfaceAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideFigure B–15 shows that the application lay

B–20 Chapter :Descriptor/Data InterfaceIP Compiler for PCI Express User Guide August 2014 Altera CorporationFigure B–16 shows how the transaction laye

Chapter : B–21Descriptor/Data InterfaceAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideIn clock cycle 3, the IP core inserts a wa

2–18 Chapter 2: Getting StartedConstraining the DesignIP Compiler for PCI Express User Guide August 2014 Altera Corporation1 The pin assignments provi

B–22 Chapter :Descriptor/Data InterfaceIP Compiler for PCI Express User Guide August 2014 Altera CorporationIn clock cycle five, the IP core asserts t

Chapter : B–23Descriptor/Data InterfaceAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideIn clock cycle five, the second transactio

B–24 Chapter :Descriptor/Data InterfaceIP Compiler for PCI Express User Guide August 2014 Altera CorporationIn clock cycles 5, 7, 9, and 11, the IP co

Chapter : B–25Descriptor/Data InterfaceAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideCompletion Interface Signals for Descripto

B–26 Chapter :Incremental Compile Module for Descriptor/Data ExamplesIP Compiler for PCI Express User Guide August 2014 Altera CorporationIncremental

Chapter : B–27Incremental Compile Module for Descriptor/Data ExamplesAugust 2014 Altera Corporation IP Compiler for PCI Express User Guide1 The ICM is

B–28 Chapter :Incremental Compile Module for Descriptor/Data ExamplesIP Compiler for PCI Express User Guide August 2014 Altera Corporation<variatio

Chapter : B–29Incremental Compile Module for Descriptor/Data ExamplesAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideICM Block Di

B–30 Chapter :Incremental Compile Module for Descriptor/Data ExamplesIP Compiler for PCI Express User Guide August 2014 Altera CorporationRX DatapathT

Chapter : B–31Incremental Compile Module for Descriptor/Data ExamplesAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideWhen using t

Chapter 2: Getting Started 2–19Compiling the DesignAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideSpecifying QSF ConstraintsThis

B–32 Chapter :Incremental Compile Module for Descriptor/Data ExamplesIP Compiler for PCI Express User Guide August 2014 Altera CorporationRX PortsTabl

Chapter : B–33Recommended Incremental Compilation FlowAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideTX PortsTable B–15 describe

B–34 Chapter :Recommended Incremental Compilation FlowIP Compiler for PCI Express User Guide August 2014 Altera Corporation1 Altera recommends disabli

Chapter : B–35Recommended Incremental Compilation FlowAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideFigure B–26 shows the appli

B–36 Chapter :Recommended Incremental Compilation FlowIP Compiler for PCI Express User Guide August 2014 Altera CorporationSideband InterfaceTable B–1

August 2014 Altera Corporation IP Compiler for PCI Express User GuideC. Performance and Resource UtilizationSoft IP ImplementationThis appendix shows

C–2 Chapter :Avalon-ST InterfaceIP Compiler for PCI Express User Guide August 2014 Altera CorporationArria II GX DevicesTable C–2 shows the typical ex

Chapter : C–3Avalon-MM InterfaceAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideStratix III FamilyTable C–4 shows the typical exp

C–4 Chapter :Descriptor/Data InterfaceIP Compiler for PCI Express User Guide August 2014 Altera CorporationTable C–6 shows the typical expected perfor

Chapter : C–5Descriptor/Data InterfaceAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideCyclone III FamilyTable C–8 shows the typic

2–20 Chapter 2: Getting StartedReusing the Example DesignIP Compiler for PCI Express User Guide August 2014 Altera CorporationReusing the Example Desi

C–6 Chapter :Descriptor/Data InterfaceIP Compiler for PCI Express User Guide August 2014 Altera CorporationStratix III FamilyTable C–10 shows the typi

August 2014 Altera Corporation IP Compiler for PCI Express User GuideAdditional InformationRevision HistoryThe table below displays the revision histo

Info–2 Chapter :Revision HistoryIP Compiler for PCI Express User Guide August 2014 Altera CorporationMay 2011 11.0 Changed IP core name to IP Compile

Chapter : Info–3Revision HistoryAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideDecember 201010.1 Added support for the followin

Info–4 Chapter :Revision HistoryIP Compiler for PCI Express User Guide August 2014 Altera CorporationJuly 2010 10.0 Added table specifying the Total

Chapter : Info–5Revision HistoryAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideNovember 20099.1 Added support for Cyclone IV GX

Info–6 Chapter :Revision HistoryIP Compiler for PCI Express User Guide August 2014 Altera CorporationFebruary 2009 9.0 Updated Table 1–8 on page 1–11

Chapter : Info–7Revision HistoryAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideNovember 20088.1 Added new material on root port

Info–8 Chapter :Revision HistoryIP Compiler for PCI Express User Guide August 2014 Altera CorporationMay 2008 8.0 Added information describing PCI Ex

Chapter : Info–9Revision HistoryAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideJune 2005 1.0.0 First release.May 2007 7.1 Add

August 2014 Altera Corporation IP Compiler for PCI Express User Guide3. Parameter SettingsYou customize the IP Compiler for PCI Express by specifying

Info–10 Chapter :How to Contact AlteraIP Compiler for PCI Express User Guide August 2014 Altera CorporationHow to Contact AlteraTo locate the most up-

Chapter : Info–11Typographic ConventionsAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideCourier typeIndicates signal, port, regis

Info–12 Chapter :Typographic ConventionsIP Compiler for PCI Express User Guide August 2014 Altera Corporation

3–2 Chapter 3: Parameter SettingsParameters in the Qsys Design FlowIP Compiler for PCI Express User Guide August 2014 Altera CorporationSystem Setting

Chapter 3: Parameter Settings 3–3Parameters in the Qsys Design FlowAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideTable 3–2 desc

1–2 Chapter 1: DatasheetFeaturesIP Compiler for PCI Express User Guide August 2014 Altera Corporation Feature rich: Support for ×1, ×2, ×4, and ×8 c

3–4 Chapter 3: Parameter SettingsParameters in the Qsys Design FlowIP Compiler for PCI Express User Guide August 2014 Altera CorporationLink Capabilit

Chapter 3: Parameter Settings 3–5Parameters in the Qsys Design FlowAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideBuffer Configu

3–6 Chapter 3: Parameter SettingsParameters in the Qsys Design FlowIP Compiler for PCI Express User Guide August 2014 Altera CorporationAvalon-MM Sett

Chapter 3: Parameter Settings 3–7Parameters in the Qsys Design FlowAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideAddress Transl

3–8 Chapter 3: Parameter SettingsIP Core ParametersIP Compiler for PCI Express User Guide August 2014 Altera CorporationHowever, bit 0 of PCIe Address

Chapter 3: Parameter Settings 3–9IP Core ParametersAugust 2014 Altera Corporation IP Compiler for PCI Express User GuidePCIe System ParametersPHY type

3–10 Chapter 3: Parameter SettingsIP Core ParametersIP Compiler for PCI Express User Guide August 2014 Altera CorporationPHY interface16-bit SDR,16-bi

Chapter 3: Parameter Settings 3–11IP Core ParametersAugust 2014 Altera Corporation IP Compiler for PCI Express User GuidePCI RegistersThe ×1 and ×4 IP

3–12 Chapter 3: Parameter SettingsIP Core ParametersIP Compiler for PCI Express User Guide August 2014 Altera CorporationBAR Table (BAR1) BAR type and

Chapter 3: Parameter Settings 3–13IP Core ParametersAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideCapabilities ParametersThe Ca

Chapter 1: Datasheet 1–3Release InformationAugust 2014 Altera Corporation IP Compiler for PCI ExpressRelease InformationTable 1–3 provides information

3–14 Chapter 3: Parameter SettingsIP Core ParametersIP Compiler for PCI Express User Guide August 2014 Altera CorporationCompletion timeout rangeRange

Chapter 3: Parameter Settings 3–15IP Core ParametersAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideMSI Capabilities0x050–0x05CMS

3–16 Chapter 3: Parameter SettingsIP Core ParametersIP Compiler for PCI Express User Guide August 2014 Altera CorporationBuffer SetupThe Buffer Setup

Chapter 3: Parameter Settings 3–17IP Core ParametersAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideNumber oflow-priority VCs0x10

3–18 Chapter 3: Parameter SettingsIP Core ParametersIP Compiler for PCI Express User Guide August 2014 Altera CorporationPower ManagementThe Power Man

Chapter 3: Parameter Settings 3–19IP Core ParametersAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideTable 3–13 describes the para

3–20 Chapter 3: Parameter SettingsIP Core ParametersIP Compiler for PCI Express User Guide August 2014 Altera CorporationAvalon-MM Configuration The A

Chapter 3: Parameter Settings 3–21IP Core ParametersAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideTable 3–14. Avalon Configurat

3–22 Chapter 3: Parameter SettingsIP Core ParametersIP Compiler for PCI Express User Guide August 2014 Altera CorporationAddress translation table siz

August 2014 Altera Corporation IP Compiler for PCI Express User Guide4. IP Core ArchitectureThis chapter describes the architecture of the IP Compiler

1–4 Chapter 1: DatasheetDevice Family SupportIP Compiler for PCI Express User Guide August 2014 Altera CorporationAltera verifies that the current ver

4–2 Chapter 4: IP Core ArchitectureApplication InterfacesIP Compiler for PCI Express User Guide August 2014 Altera CorporationFigure 4–1 broadly descr

Chapter 4: IP Core Architecture 4–3Application InterfacesAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideThe PCI Express Avalon-S

4–4 Chapter 4: IP Core ArchitectureApplication InterfacesIP Compiler for PCI Express User Guide August 2014 Altera CorporationFigure 4–3 and Figure 4–

Chapter 4: IP Core Architecture 4–5Application InterfacesAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideTable 4–1 provides the a

4–6 Chapter 4: IP Core ArchitectureApplication InterfacesIP Compiler for PCI Express User Guide August 2014 Altera CorporationRX DatapathThe RX datapa

Chapter 4: IP Core Architecture 4–7Application InterfacesAugust 2014 Altera Corporation IP Compiler for PCI Express User Guide1 The value of the non-p

4–8 Chapter 4: IP Core ArchitectureApplication InterfacesIP Compiler for PCI Express User Guide August 2014 Altera CorporationFigure 4–5 illustrates t

Chapter 4: IP Core Architecture 4–9Transaction LayerAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideFigure 4–6 shows the block di

4–10 Chapter 4: IP Core ArchitectureTransaction LayerIP Compiler for PCI Express User Guide August 2014 Altera Corporation5. The receive sequencing an

Chapter 4: IP Core Architecture 4–11Transaction LayerAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideTracing a transaction throug

Chapter 1: Datasheet 1–5General DescriptionAugust 2014 Altera Corporation IP Compiler for PCI ExpressThe hard IP implementation includes all of the re

4–12 Chapter 4: IP Core ArchitectureData Link LayerIP Compiler for PCI Express User Guide August 2014 Altera CorporationData Link LayerThe data link l

Chapter 4: IP Core Architecture 4–13Data Link LayerAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideThe data link layer has the fo

4–14 Chapter 4: IP Core ArchitecturePhysical LayerIP Compiler for PCI Express User Guide August 2014 Altera CorporationPhysical LayerThe physical laye

Chapter 4: IP Core Architecture 4–15Physical LayerAugust 2014 Altera Corporation IP Compiler for PCI Express User GuidePhysical Layer ArchitectureFigu

4–16 Chapter 4: IP Core ArchitecturePhysical LayerIP Compiler for PCI Express User Guide August 2014 Altera CorporationThe PHYMAC block is divided in

Chapter 4: IP Core Architecture 4–17PCI Express Avalon-MM BridgeAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideReverse Parallel

4–18 Chapter 4: IP Core ArchitecturePCI Express Avalon-MM BridgeIP Compiler for PCI Express User Guide August 2014 Altera CorporationFigure 4–10 shows

Chapter 4: IP Core Architecture 4–19PCI Express Avalon-MM BridgeAugust 2014 Altera Corporation IP Compiler for PCI Express User Guide Transmitted ups

4–20 Chapter 4: IP Core ArchitecturePCI Express Avalon-MM BridgeIP Compiler for PCI Express User Guide August 2014 Altera Corporation1 To improve PCI

Chapter 4: IP Core Architecture 4–21PCI Express Avalon-MM BridgeAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideAs an example, Ta

1–6 Chapter 1: DatasheetGeneral DescriptionIP Compiler for PCI Express User Guide August 2014 Altera Corporation Physical Coding Sublayer (PCS) Medi

4–22 Chapter 4: IP Core ArchitecturePCI Express Avalon-MM BridgeIP Compiler for PCI Express User Guide August 2014 Altera CorporationFigure 4–11 depic

Chapter 4: IP Core Architecture 4–23PCI Express Avalon-MM BridgeAugust 2014 Altera Corporation IP Compiler for PCI Express User Guidespecifies 32-bit

4–24 Chapter 4: IP Core ArchitecturePCI Express Avalon-MM BridgeIP Compiler for PCI Express User Guide August 2014 Altera CorporationFigure 4–12 depic

Chapter 4: IP Core Architecture 4–25PCI Express Avalon-MM BridgeAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideIn Qsys-generated

4–26 Chapter 4: IP Core ArchitectureCompleter Only PCI Express Endpoint Single DWordIP Compiler for PCI Express User Guide August 2014 Altera Corporat

Chapter 4: IP Core Architecture 4–27Completer Only PCI Express Endpoint Single DWordAugust 2014 Altera Corporation IP Compiler for PCI Express User Gu

4–28 Chapter 4: IP Core ArchitectureCompleter Only PCI Express Endpoint Single DWordIP Compiler for PCI Express User Guide August 2014 Altera Corporat

August 2014 Altera Corporation IP Compiler for PCI Express User Guide5. IP Core InterfacesThis chapter describes the signals that are part of the IP C

5–2 Chapter 5: IP Core InterfacesAvalon-ST InterfaceIP Compiler for PCI Express User Guide August 2014 Altera Corporationrx_st_ready0rx_st_valid0rx_st

Chapter 5: IP Core Interfaces 5–3Avalon-ST InterfaceAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideFigure 5–2. Signals in the Ha

Chapter 1: Datasheet 1–7General DescriptionAugust 2014 Altera Corporation IP Compiler for PCI ExpressThe IP Compiler for PCI Express supports ×1, ×2,

5–4 Chapter 5: IP Core InterfacesAvalon-ST InterfaceIP Compiler for PCI Express User Guide August 2014 Altera CorporationFigure 5–3. Signals in the So

Chapter 5: IP Core Interfaces 5–5Avalon-ST InterfaceAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideTable 5–1 lists the interface

5–6 Chapter 5: IP Core InterfacesAvalon-ST InterfaceIP Compiler for PCI Express User Guide August 2014 Altera Corporation64- or 128-Bit Avalon-ST RX P

Chapter 5: IP Core Interfaces 5–7Avalon-ST InterfaceAugust 2014 Altera Corporation IP Compiler for PCI Express User Guiderx_st_err<n>1OerrorIndi

5–8 Chapter 5: IP Core InterfacesAvalon-ST InterfaceIP Compiler for PCI Express User Guide August 2014 Altera CorporationTo facilitate the interface t

Chapter 5: IP Core Interfaces 5–9Avalon-ST InterfaceAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideTable 5–3 shows the byte orde

5–10 Chapter 5: IP Core InterfacesAvalon-ST InterfaceIP Compiler for PCI Express User Guide August 2014 Altera CorporationFigure 5–6 illustrates the m

Chapter 5: IP Core Interfaces 5–11Avalon-ST InterfaceAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideFigure 5–8 shows the mapping

5–12 Chapter 5: IP Core InterfacesAvalon-ST InterfaceIP Compiler for PCI Express User Guide August 2014 Altera CorporationFigure 5–10 shows the mappin

Chapter 5: IP Core Interfaces 5–13Avalon-ST InterfaceAugust 2014 Altera Corporation IP Compiler for PCI Express User GuideFigure 5–12 shows the mappin