Altera SDI II MegaCore Manual do Utilizador

SDI II IP Core User GuideLast updated for Altera Complete Design Suite: 15.0SubscribeSend FeedbackUG-011252015.05.04101 Innovation DriveSan Jose, CA 9

Figure 2-3: Example of 3G-SDI (Level B) to HD-SDI Dual Link ConversionThe figure shows the conversion of 3G-SDI (level B) data to two HD-SDI data stre

SMPTE RP168 Switching SupportThe SMPTE RP168 standard defines the requirements for synchronous switching between two videosources to take place with m

Dynamic TX Clock SwitchingThe dynamic TX clock switching feature allows you to dynamically switch between NTSC and PALtransceiver data rates for all v

Figure 2-7: Hardware Implementation of the Dynamic TX Clock Switching FeatureThe figure shows the TX clock switching feature with two TX PLLs.TX Proto

Table 2-2: Dynamic Switching Behavior During a Handshaking ProcessCase Description1 The handshaking process attempts to switch to select xcvr_refclk_a

Standard ALM Needed Primary LogicRegistersSecondary LogicRegistersBlock Memory BitsHD Dual Link TX 367 410 60 0HD Dual Link RX 1,239 1,780 177 4,6083G

SDI II IP Core Getting Started32015.05.04UG-01125SubscribeSend FeedbackInstallation and LicensingTo evaluate the SDI II IP core using the OpenCore Plu

This walkthrough includes the following steps:1. Creating a New Quartus II Project on page 3-22. Launching IP Catalog on page 3-23. Parameterizing the

Parameterizing the IP CoreTo parameterize your IP core, follow these steps:1. Select the video standard.2. Select Bidirectional, Transmitter, or Recei

Simulator Supported Platform Supported LanguageAldec Riviera-PRO Linux VerilogTo simulate the design using the ModelSim-SE or ModelSim-Altera simulato

ContentsSDI II IP Core Quick Reference...1-1SDI II IP Core Overview...

• Design Examples on page 3-9Each design example provided with the SDI II IP core is synthesizable.• Quartus II HelpMore information about compilation

SDI II IP Core ParametersTable 3-2: SDI II IP Core ParametersParameter Value DescriptionConfigurationOptionsVideo standardSD-SDI, HD-SDI,3G-SDI, HD-SD

Parameter Value DescriptionTransceiverOptions(2)Dynamic Tx clockswitchingOff, Tx PLLsswitching, Tx PLLreference clocksswitching• Off: Disable dynamic

Parameter Value DescriptionExtract PayloadID (SMPTE352M)On, Off • On: Extract payload ID• Off: No payload ID extraction (saves logic)It is compulsory

SDI II IP Core Component FilesTable 3-3: Generated FilesTable below describes the generated files and other files that might be in your project direct

Figure 3-1: Design Example Entity and Simulation Testbench for Arria 10 DevicesLoopbackPathCh0 Loopback(SDI TX + RX)Arria 10 NativePHY (Duplex)Ch0 RXT

This design generates two transceiver PHY reset controllers—one for TX and one for RX. These resetcontrollers are connected to the transceiver to cont

Figure 3-2: Design Example Entity and Simulation TestbenchLoopbackPathCh0Loopback(SDI Duplex)ReconfigurationManagement/RouterCh1 Test(SDI RX)Ch1 DUT(S

Figure 3-3: Design Example Entity and Simulation Testbench for HD-SDI Dual Link to 3G-SDI (Level B)ConversionThe figure below illustrates the generate

Figure 3-4: Design Example Entity and Simulation Testbench for 3G-SDI (Level B) to HD-SDI Dual LinkConversionThe figure below illustrates the generate

TX Sample...4-18Cl

The Arria 10 design example for the SDI II IP core consists of the following components:• Video pattern generator• Transceiver reconfiguration control

Transceiver Reconfiguration Controller for Arria V, Cyclone V, and Stratix VFor Arria V, Cyclone V, and Stratix V design examples, the transceiver rec

Since only one transceiver register can be accessed at a time, the whole process repeats when reconfi‐guring other registers.For multiple SDI channels

Avalon-MM TranslatorsThe Avalon-MM Master Translator and Avalon-MM Slave Translator are Avalon-MM interface blocksthat access the Transceiver Reconfig

The following sequence of events occur when there is a change in the SDI receiver video standard:1. The SDI receiver locks to 3G-SDI standard and dete

.number_of_reconfig_interfaces (7), ….) u_reconfig ( .reconfig_to_xcvr ({reconfig_to_xcvr_du_ch2, reconfig_to_xcvr

Table 3-7: Logical Channel Number For Each SDI ChannelSDI Channel Direction Number of ReconfigurationInterfacesLogical Channel Number0 Duplex 2 • 0: R

between the SDI instance and the transceiver reconfiguration controller or the reconfigurationmanagement.Video Pattern Generator SignalsTable 3-8: Vid

Signal Width Direction Descriptionpattgen_patho1 Input Set to 1 to generate pathological pattern.pattgen_blank1 Input Set to 1 to generate black signa

Signal Width Direction Descriptionxcvr_reconfig_rst 1 Input Reset signal for reconfiguration user logic.This signal is active high and level sensitive

SDI II IP Core Quick Reference12015.05.04UG-01125SubscribeSend FeedbackThe Altera® Serial Digital Interface (SDI) II MegaCore® function is the next ge

Signal Width Direction Descriptionpll_sel 1 Input Signal to specify which TX PLL to use. Thissignal must share the same source as pll_select signal in

Related Information• Transceiver Reconfiguration Controller on page 3-15The transceiver reconfiguration controller reconfigures the transceivers. The

Related Information• Reconfiguration Management on page 3-16• Modifying the Reconfiguration Management on page 3-20Reconfiguration Router SignalsTable

SDI II IP Core Functional Description42015.05.04UG-01125SubscribeSend FeedbackThe SDI II IP core implements a transmitter, receiver, or full-duplex in

Figure 4-2: SDI II IP Core Block Diagram for Arria 10 DevicesSDI II IP Core for Arria 10Parallel Video InParallel Video OutSDI OutSDI InProtocolPHY Re

Figure 4-3: SD-SDI Transmitter Data Path Block DiagramMatchTRSInsertPayload IDScramblerTXOversampleGenerateClock EnableTransmitTX Protocol TX PHY Mana

Figure 4-6: Dual Link HD-SDI Transmitter Data Path Block DiagramMatchTRSInsertLineScramblerInsertLineMultiplexer20TransmitTX ProtocolTX PHY Management

Figure 4-7: Triple Rate SDI Transmitter Data Path Block DiagramMatchTRSInsertLineScramblerInsertLine20Multiplexer2020TXOversampleGenerateClock EnableT

Figure 4-8: Multi Rate (up to 12G-SDI) Transmitter Data Path Block DiagramNote: The transmit block shown in the diagram is the simplified version of t

• HD-SDI LN extraction• HD-SDI CRC• Payload ID extraction• Synchronizing data streams• Accessing transceiver• Identifying and tracking of ancillary da

Item DescriptionFeatures • 20-bit interface support for SD-SDI• Multiple SDI standards and video formats• Payload identification packet insertion and

Figure 4-11: 3G-SDI Receiver Data Path Block DiagramDetectFormatTRSAlignerDescramblerDetect1 & 1/1,001RateTransceiverControlStateMachineReceivePre

Figure 4-13: Dual Link HD-SDI Receiver Data Path Block DiagramDetectFormatDetect1 & 1/1,001RateTransceiverControlStateMachineReceiveRX ProtocolRX

Figure 4-14: Triple Rate SDI Receiver Data Path Block DiagramDetectVideoStandardTransceiverControlStateMachineTransceiverDetectFormatTRSAlignerDescram

Figure 4-15: Multi Rate (up to 12G-SDI) Receiver Data Path Block DiagramNote: The receive block shown in the diagram is the simplified version of the

Figure 4-16: SD-SDI Duplex Mode Block DiagramTX ProtocolDetectFormatTRSAlignerDescramblerRXOversampleTransceiverControlState MachineReceive PrealignRX

Figure 4-17: Altera Native PHY IP Core Setup in Duplex ModeThe Altera Native PHY IP Core does not include an embedded reset controller and an Avalon-M

SubmodulesYou can reuse the submodules in the protocol and transceiver components across different videostandard. The SDI II IP core consists of the f

Figure 4-18: Line Number Insertion and Signal RequirementsFigure below illustrates the line number insertion and signal requirements. For a correct li

Video Format Field Line Number625i1 92 3221080i1 102 572525p — 13625p — 9720p — 101080p — 10For dual link HD-SDI interface, the payload ID packets are

Match TRSThis submodule indicates that the current word is a particular TRS word in both the transmitter andreceiver. This submodule has the following

SDI II IP Core Overview22015.05.04UG-01125SubscribeSend FeedbackThe SDI II IP core implements a transmitter, receiver, or full-duplex SDI at standard

TX SampleThe TX sample submodule is a transmit oversampling block. It repeats each bit of the input word a givennumber of times and constructs the out

Figure 4-20: Triple Rate Transmit Clocking SchemeFigure below illustrates the behavior of the tx_datain_valid pulse in each video standard.tx_pclk(148

Table 4-3: Sampling ProcessThe submodule executes the sampling process in the following manner.Step Process Description1 Detect transitions in the inc

Detect Video StandardThe detect video standard submodule performs coarse rate detection on the incoming video stream fordual, triple, or multi rate SD

The transceiver controller uses a different approach to detect the incoming video standard. Instead ofsetting the core to each of the standards and wa

TRS AlignerThe TRS aligner word aligns the descrambled receiver data until the bit order of the output data and theoriginal video data are the same. T

3Gb DemuxThis submodule demultiplex the Y link A, C link A, Y link B, and C link B from the received 20-bit datafor further processing. This submodule

This submodule implements a pixel counter and a line counter. These counters are driven from the pixelclock and synchronous pulses. The basic approach

Convert SD BitsThis submodule is enabled when you set the SD Interface Bit Width parameter option to 20. Thissubmodule converts the SD parallel data i

Figure 4-23: Sync Bits Insertion ProcessEAV 3FD (C)EAV 3FD (C)EAV 3FD (C)EAV 3FD (C)EAV 3FD (Y)EAV 3FD (Y)EAV 3FD (Y)EAV 3FF (Y)EAV 000 (C)EAV 000 (C)

• Triple standard support for SD-SDI, HD-SDI, and 3G-SDI• Multi standard support for SD-SDI, HD-SDI, 3G-SDI, 6G-SDI, and 12G-SDI• SMPTE425M level A su

Table 4-5: Transmitter Protocol SignalsNote: S = Indicates the number of streams; 4 for multi standard (up to 12G) mode and 1 for other modes.Signal W

Signal Width Direction Descriptiontx_datain20S Input User-supplied transmitter parallel data.• SD-SDI = bits 19:10 unused; bits 9:0 C, Y, Cr, Y multip

Signal Width Direction Descriptiontx_trs_b1 Input Transmitter TRS input for link B. For use in HD-SDI dual linkmode LN, CRC, or payload ID insertion.

Signal Width Direction Descriptiontx_vpid_byte38S Input The core inserts payload ID byte 3.Applicable only when you enable the Insert Payload ID (SMPT

Table 4-6: Receiver Protocol SignalsNote: S = Indicates the number of streams; 4 for multi standard (up to 12G) mode and 1 for other modes.Signal Widt

Signal Width Direction Descriptionrx_dataout_valid1 Output Data valid from the oversampling logic. The receiver asserts thissignal to indicate current

Signal Width Direction Descriptionrx_format5 Output Indicates the format for the received video transport.• SMPTE259M 525i = 00000• SMPTE259M 625i = 0

Signal Width Direction Descriptionrx_trs_locked1S Output TRS locked, indicating that six consecutive TRSs with sametiming has been spotted.rx_frame_lo

Signal Width Direction Descriptionrx_line_f011S Output Line number of field 0 (F0) of the payload ID location. Requirestwo complete frames to update t

Signal Width Direction Descriptionrx_vpid_checksum_error1S Output Indicates that the extracted payload ID has a checksum error.Applicable only when yo

Figure 2-1: Example of HD-SDI Dual Link to 3G-SDI (Level B) ConversionThe figure shows the conversion of two HD-SDI data streams to 3G-SDI (level B) d

Table 4-7: Transceiver (PHY Management, PHY Adapter, and Hard Transceiver) SignalsSignal Width Direction Descriptionrx_rst1 Input Reset signal for the

Signal Width Direction Descriptionxcvr_refclk_alt1 Input Alternative clock input for the hard transceiver. The frequency ofthis signal must be the alt

Signal Width Direction Descriptionreconfig_to_xcvr70N Input Dynamic reconfiguration input for the hard transceiver, where Nis the reconfiguration inte

Signal Width Direction Descriptiontx_rst1 Input Reset signal for the transmitter. This signal is active high andlevel sensitive. This reset signal mus

Signal Width Direction Descriptionrx_clkout_is_ntsc_paln1 Input Indicates the video rate received. Applicable for all modes exceptSD-SDI.• 0 = PAL rat

Signal Width Direction Descriptiontx_dataout_valid1 Output Data valid generated by the core. This signal can be used to drivetx_datain_valid. The timi

Signal Width Direction Descriptiongxb_ltr1 Output Control signal to the transceiver rx_set_locktoref input signal.Assert this signal to program the Rx

Additional InformationA2015.05.04UG-01125SubscribeSend FeedbackAdditional information about the document and Altera.Document Revision HistoryDate Vers

Date Version Changes• Added information for multi standard support including 6G-SDI and12G-SDI.• Added the multi standard (including 6G-SDI and 12G-SD

Date Version ChangesAugust 2014 2014.08.18• Added support for Arria 10 devices.• Revised the resource utilization table with information about ALMneed

Figure 2-2: Implementation of HD-SDI Dual Link to 3G-SDI (Level B) ConversionThe figure shows a block diagram of HD-SDI dual link to 3G-SDI (level B)