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Introduction to Avalon Verification IP Suite

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The Avalon

Verification IP Suite provides bus functional models (BFMs) to simulate the behavior and

facilitate the verification of IP. The Verification IP Suite includes BFMs for the following interfaces and

components:

• Avalon Memory-Mapped (Avalon-MM) master and slave interfaces

• Avalon Streaming (Avalon-ST) source and sink interfaces

• Conduit interfaces and Avalon Tri-State conduit (Avalon-TC) interfaces

• Clock source and reset source

• Interrupt source and sink

• Custom instruction master and slave

• External memory

This suite also provides the following monitors to verify the respective Avalon protocols:

• Avalon-MM monitor

• Avalon-ST monitor

Advantages of Using BFMs and Monitors

Using the Altera-provided BFMs and monitors has the following advantages:

• It accelerates the verification process by providing key components of the verification testbench.

• It provides Avalon BFM components that implement the standard Avalon-MM and Avalon-ST protocols,

serving as a reference for those protocols.

• For SystemVerilog users, the verification suite provides a platform that you can use to implement

constraint-driven randomized tests. For example, you can implement the following modules for random

testing:

• Traffic scenario drivers

• Scoreboard and coverage facilities

• Assertion checkers

BFM Implementation

Most components in the Avalon Verification IP Suite BFMs are implemented in SystemVerilog. The exceptions

are the Clock Source and Reset Source BFMs that are written in VHDL. The BFM components use primarily

ISO

9001:2008

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Altera Avalon Verification IP Suite Manual do Utilizador Página 12