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Values

Default

Value

Parameter

Port Widths

Data symbol width in bits. The symbol width should

be 8 for byte-oriented interfaces.

1–10248Symbol Width

Specifies the number of symbols that are transferred

per beat.

1–10244Number of symbols

Specifies the width of the channel signal.1–321Width of the channel port

Specifies the width of the error signal.1–10241Width of the error port

Specifies the width of the empty signal.1–10241Width of the empty port

Timing Attributes

Specifies the delay between the ready and valid

signals.

For more information about the ready and valid

signals, refer to the Avalon Interface Specification.

0–80Ready latency

Specifies the number of beats per cycle.1–10241Number of beats per cycle

Channel Attributes

Specifies the maximum number of channels that the

interface supports.

—1Max channel number

Miscellaneous

For VHDL BFMs only. Use this option to assign a

unique number to each BFM in the testbench design.

0–10230VHDL BFM ID

Related Information

Avalon Interface Specification

Avalon-ST Source API

event_max_transaction_queue_size()

event_max_transaction_queue_size()Prototype:

Verilog HDL: N.A.

VHDL: bfm_id

Arguments:

voidReturns:

Notifies the testbench that the transaction queue exceeds the maximum level.Description:

VHDLLanguage support:

Avalon-ST Source BFM

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