Altera Avalon Verification IP Suite Manual do Utilizador descarregar pdf (Página 214)

Running the Verilog HDL Testbench for the Two Avalon-MM Masters and Slaves

1. Unzip ug_avalon_verification.zip to a working directory.

2. Open <working_dir>/avlm_avls_2x2.qsys.

3. Complete the following steps to generate the testbench:

a. On the Generate menu, select Generate HDL.

b. Specify the parameters shown in the following table:

Table 17-2: Generation Parameters

ValueParameter

Synthesis

Leave this option offCreate HDL design files for synthesis

Leave this option offCreate timing and resource estimates for third-party

EDA synthesis tools

Leave this option onCreate block symbol file (.bsf)

Simulation

VerilogCreate simulation model

Leave this option offAllow mixed-language simulation

Output Directory

<working_dir>/avlm_avls_2x2Path

c. Click Generate.

The Qsys Generate window displays informational messages as it generates the testbench.

d. Close the Generate window.

4. Start the ModelSim simulator.

5. To run the simulation, type the following command in your working directory:

do run_simulation.tcl

This command compiles all the required HDL files, elaborates, and runs the simulation.

Avalon-MM Verilog HDL and VHDL Testbenches

Altera Corporation

Send Feedback

Running the Verilog HDL Testbench for the Two Avalon-MM Masters and Slaves

17-4

1 2 ... 209 210 211 212 213 214 215 216 217 218 219 ... 223 224

Sem comentários

Altera Avalon Verification IP Suite Manual do Utilizador Página 214