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be designated as prefetchable or non-prefetchable in Qsys. Finally, the address range of VF BAR 0 can be
configured as any power of 2 between 128 bytes and 2 Gbytes.
The contents of VF BAR 0 are described below:
Table 5-37: VF BARs 0 - 5, 0x1A4 - 0x1B0
Bits Register Description Default Value Access
[0] Memory Space Indicator: Hardwired to 0 to indicate the BAR
defines a memory address range.
0 RO
[1] Reserved. Hardwired to 0. 0
[2] Specifies the BAR size.: The following encodings are defined:
• 1'b0: 32-bit BAR
• 1'b1: 64-bit BAR created by pairing BAR0 with BAR1, BAR2
with BAR3, or BAR4 with BAR5
0
RO
[3] When 1, indicates that the data within the address range refined
by this BAR is prefetchable. When 1, indicates that the data is not
prefetchable. Data is prefetchable if reading is guaranteed not to
have side-effects .
Prefetchable: 0;
Non-Prefetch‐
able: 1
RO
[7:4] Reserved. Hardwired to 0. 0 RO
[31:8] Base address of the BAR. The number of writeable bits is based on
the BAR access size. For example, if bits [15:8] are hardwired to 0,
if the BAR access size is 64 Kbytes. Bits [31:16] can be read and
written.
0
See
description
Secondary PCI Express Extended Capability Header
Table 5-38: Secondary PCI Express Extended Capability Header - 0x200
Bits Register Description Default Value Access
[15:0] PCI Express Extended Capability ID. 0x0019 RO
[19:16] Capability Version. 0x1 RO
[31:20] Next Capability Pointer. Points to NULL. Variable RO
UG-01097_sriov
2014.12.15
Secondary PCI Express Extended Capability Header
5-23
Registers
Altera Corporation
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- User Guide 1
- Datasheet 2
- Features 3
- Interface 4
- Release Information 7
- Device Family Support 7
- Example Designs 8
- Debug Features 8
- IP Core Verification 9
- Recommended Speed Grades 10
- Related Information 11
- Subscribe 12
- Qsys Subsystem Description 13
- Parameter Value 15
- Directory Description 16
- Parameter Settings 21
- Parameter Value Description 22
- SR-IOV System Settings 24
- Interrupt Capabilities 27
- Device Capabilities 29
- Error Reporting 30
- Link Capabilities 31
- Slot Capabilities 32
- Power Management 33
- PHY Characteristics 34
- Simulation Options 35
- Avalon-ST TX Interface 37
- Signal Direction Description 38
- Avalon‑ST RX Interface 40
- BAR Hit Signals 43
- Completion Side Band Signals 45
- Signal Directi 46
- Description 46
- Clock Signals 48
- Interrupt Interface 49
- Implementing MSI-X Interrupts 55
- LMI Signals 57
- Serial Data Signals 65
- Test Signals 70
- PIPE Interface Signals 71
- Byte Address 77
- MSI Registers 80
- MSI-X Capability Structure 82
- VF Device ID Register 96
- Page Size Registers 96
- Lane Error Status Register 98
- Bits Register Description 99
- Default Value 99
- Altera Corporation 100
- Registers 100
- Send Feedback 100
- Virtual Function Registers 102
- Name Description 103
- Reset and Clocks 107
- Hard IP for PCI Express 108
- Example Design 108
- UG-01097_sriov 109
- 2014.12.15 109
- Function Level Reset (FLR) 111
- Clock Domains 111
- Clock Summary 114
- Interrupts 115
- Error Handling 118
- Physical Layer Errors 119
- Data Link Layer Errors 119
- Transaction Layer Errors 120
- Error Type Description 121
- Status Bit Conditions 123
- IP Core Architecture 125
- Top-Level Interfaces 126
- Clocks and Reset 126
- Transceiver Reconfiguration 126
- Data Link Layer 127
- Physical Layer 129
- TX Packets 130
- Design Implementation 136
- CONF_DONE 137
- Endpoint Reset 137
- Root Port Reset 137
- SDC Timing Constraints 138
- Debugging 143
- Setting Up Simulation 146
- Use Third-Party PCIe Analyzer 148
- BIOS Enumeration Issues 148
- Address[31:2] 149
- Figure A-6: I/O Read Request 151
- Additional Information 155
- Typographic Conventions 156
- Visual Cue Meaning 157
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