Altera Stratix V Avalon-ST Manual do Utilizador descarregar pdf (Página 40)

Signal Direction Description

tx_cred_hdrfccp[7:0]

Output Header credit limit for the FC completions. Each credit is 20

bytes.

tx_cred_hdrfcnp[7:0]

Output Header limit for the non-posted requests. Each credit is 20 bytes.

tx_cred_hdrfcp[7:0]

Output Header credit limit for the FC posted writes. Each credit is 20

bytes.

Avalon‑ST RX Interface

Table 4-3: 128- or 256‑Bit Avalon-ST RX Datapath

Signal Direction Description

rx_st_data[<n>-1:0]

Output Receive data bus. Refer to figures following this table for the

mapping of the Transaction Layer’s TLP information to rx_st_

data and examples of the timing of this interface. Note that the

position of the first payload dword depends on whether the TLP

address is qword aligned. The mapping of message TLPs is the

same as the mapping of TLPs with 4-dword headers. When using

a 128-bit Avalon-ST bus, the width of rx_st_data is 128. When

using a 256-bit Avalon-ST bus, the width of rx_st_data is 256

bits.

rx_st_sop

Output

Indicates that this is the first cycle of the TLP when rx_st_valid

is asserted.

rx_st_eop Output Indicates that this is the last cycle of the TLP when rx_st_valid

is asserted.

rx_st_empty[1:0]

Output Indicates the number of empty qwords in rx_st_data. Valid

only when rx_st_eop is asserted in 128-bit and 256-bit modes.

For 128-bit data, only bit 0 applies; this bit indicates whether the

upper qword contains data. For 256-bit data single packet per

cycle mode, both bits are used to indicate whether 0-3 upper

UG-01097_sriov

2014.12.15

Avalon‑ST RX Interface

4-5

Interfaces and Signal Descriptions

Altera Corporation

Send Feedback

1 2 ... 35 36 37 38 39 40 41 42 43 44 45 ... 157 158

Sem comentários

Altera Stratix V Avalon-ST Manual do Utilizador Página 40