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PCI Express Capability Structure
Figure 5-5: PCI Express Capability Structure - Byte Address Offsets and Layout
In the following table showing the PCI Express Capability Structure, registers that are not applicable to a
device are reserved.
0x080
0x084
0x088
0x08C
0x090
0x094
0x098
0x09C
0x0A0
0x0A4
0x0A8
0x0AC
0x0B0
PCI Express Capabilities Register Next Cap Pointer
Device Capabilities
Device Status Device Control
Slot Capabilities
Root Status
Device Compatibilities 2
Link Capabilities 2
Link Status 2
Link Control 2
31
24
23
16
15
8
7
0
PCI Express
Capabilities ID
Link Capabilities
Link Status Link Control
Slot Status
Slot Control
Device Status 2 Device Control 2
Root Capabilities
Root Control
Table 5-12: PCI Express Capability Register - 0x080
Bits Description Default Value Access
[31:19] Reserved 0 RO
[18:16] Version ID: Version of Power Management Capability. 0x3 RO
[15:8] Next Capability Pointer: Points to the PCI Express Capability. 0x80 RO
[7:0] Capability ID assigned by PCI-SIG. 0x01 RO
Table 5-13: PCI Express Device Capabilities Register -0x084
Bits Description Default Value Access
[2:0] Maximum Payload Size supported by the Function. Can be
configured as 000 (128 bytes) or 001 (256 bytes)
Set in Qsys RO
[4:3] Reserved 0 RO
[5] Extended tags supported Set in Qsys RO
[8:6] Acceptable L0S latency 0 RO
[11:9] Acceptable L1 latency 0 RO
[14:12] Reserved 0 RO
UG-01097_sriov
2014.12.15
PCI Express Capability Structure
5-11
Registers
Altera Corporation
Send Feedback
- User Guide 1
- Datasheet 2
- Features 3
- Interface 4
- Release Information 7
- Device Family Support 7
- Example Designs 8
- Debug Features 8
- IP Core Verification 9
- Recommended Speed Grades 10
- Related Information 11
- Subscribe 12
- Qsys Subsystem Description 13
- Parameter Value 15
- Directory Description 16
- Parameter Settings 21
- Parameter Value Description 22
- SR-IOV System Settings 24
- Interrupt Capabilities 27
- Device Capabilities 29
- Error Reporting 30
- Link Capabilities 31
- Slot Capabilities 32
- Power Management 33
- PHY Characteristics 34
- Simulation Options 35
- Avalon-ST TX Interface 37
- Signal Direction Description 38
- Avalon‑ST RX Interface 40
- BAR Hit Signals 43
- Completion Side Band Signals 45
- Signal Directi 46
- Description 46
- Clock Signals 48
- Interrupt Interface 49
- Implementing MSI-X Interrupts 55
- LMI Signals 57
- Serial Data Signals 65
- Test Signals 70
- PIPE Interface Signals 71
- Byte Address 77
- MSI Registers 80
- MSI-X Capability Structure 82
- VF Device ID Register 96
- Page Size Registers 96
- Lane Error Status Register 98
- Bits Register Description 99
- Default Value 99
- Altera Corporation 100
- Registers 100
- Send Feedback 100
- Virtual Function Registers 102
- Name Description 103
- Reset and Clocks 107
- Hard IP for PCI Express 108
- Example Design 108
- UG-01097_sriov 109
- 2014.12.15 109
- Function Level Reset (FLR) 111
- Clock Domains 111
- Clock Summary 114
- Interrupts 115
- Error Handling 118
- Physical Layer Errors 119
- Data Link Layer Errors 119
- Transaction Layer Errors 120
- Error Type Description 121
- Status Bit Conditions 123
- IP Core Architecture 125
- Top-Level Interfaces 126
- Clocks and Reset 126
- Transceiver Reconfiguration 126
- Data Link Layer 127
- Physical Layer 129
- TX Packets 130
- Design Implementation 136
- CONF_DONE 137
- Endpoint Reset 137
- Root Port Reset 137
- SDC Timing Constraints 138
- Debugging 143
- Setting Up Simulation 146
- Use Third-Party PCIe Analyzer 148
- BIOS Enumeration Issues 148
- Address[31:2] 149
- Figure A-6: I/O Read Request 151
- Additional Information 155
- Typographic Conventions 156
- Visual Cue Meaning 157
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