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This interface also includes signals to set and clear the individual bits in the MSI Pending Bit Register.
Table 4-8: MSI Interrupts
Signal Direction Description
app_msi_req Input When asserted, the Application Layer is requesting that an MSI
interrupt be sent. Assertion causes an MSI posted write TLP to be
generated. The MSI TLP uses app_msi_req_fn[7:0], app_msi_
tc and app_msi_num to create the TLP. Refer to Figure 4-1 for a
timing diagram.
app_msi_req_fn[7:0] Input Specifies the function generating the MSI or MSI-X interrupt.
Driven in the same cycle as app_msi_req or app_msix_req.
app_msi_ack Output Ack for MSI interrupts. When asserted, indicates that Hard IP
has sent an MSI posted write TLP in response app_msi_req . The
Application Layer must wait for app_msi_ack after asserting
app_msi_req. The Application Layer must de-assert app_msi_
req for at least 1 cycle before signaling a new MSI interrupt.
app_msi_addr_
pf[127:0]
Output
Driven by the MSI address registers of PF0 and PF1. app_msi_
addr_pf[63:0] specifies the PF0 address. app_msi_addr_
pf[127:64] specifies the PF1 address.
app_msi_data_pf[16<n>
-1:0]
Output
Driven by the MSI Data Registers of PF0 and PF1. <n>= the
number of PFs.
app_msi_enable_
pf[1:0]
Output Driven by the MSI Enable bit of the MSI Control Registers of PF0
and PF1.
app_msi_mask_pf[32<n>
-1:0]
Output
The MSI Mask Bits of the MSI Capability Structure drive app_
msi_mask_pf. This mask allows software to disable or defer
message sending on a per-vector basis. app_msi_mask_pf[31:0]
mask vectors for PF0.app_msi_mask_pf[63:32] mask vectors
for PF1.
app_msi_multi_msg_
enable_pf[5:0]
Output Defines the number of interrupt vectors enabled for each PF. The
following encodings are defined:
• 3'b000: 1 vector
• 3'b001: 2 vectors
• 3'b010: 4 vectors
• 3'b100: 16 vectors
• 3'b101: 32 vectors
The MSI Multiple Message Enable field of the MSI Control
Register of PF0 drives app_msi_multi_msg_enable_pf[2:0].
The MSI Multiple Message Enable field of the MSI Control
Register of PF1 drives app_msi_multi_msg_enable_pf[5:3].
UG-01097_sriov
2014.12.15
Interrupt Interface
4-15
Interfaces and Signal Descriptions
Altera Corporation
Send Feedback
- User Guide 1
- Datasheet 2
- Features 3
- Interface 4
- Release Information 7
- Device Family Support 7
- Example Designs 8
- Debug Features 8
- IP Core Verification 9
- Recommended Speed Grades 10
- Related Information 11
- Subscribe 12
- Qsys Subsystem Description 13
- Parameter Value 15
- Directory Description 16
- Parameter Settings 21
- Parameter Value Description 22
- SR-IOV System Settings 24
- Interrupt Capabilities 27
- Device Capabilities 29
- Error Reporting 30
- Link Capabilities 31
- Slot Capabilities 32
- Power Management 33
- PHY Characteristics 34
- Simulation Options 35
- Avalon-ST TX Interface 37
- Signal Direction Description 38
- Avalon‑ST RX Interface 40
- BAR Hit Signals 43
- Completion Side Band Signals 45
- Signal Directi 46
- Description 46
- Clock Signals 48
- Interrupt Interface 49
- Implementing MSI-X Interrupts 55
- LMI Signals 57
- Serial Data Signals 65
- Test Signals 70
- PIPE Interface Signals 71
- Byte Address 77
- MSI Registers 80
- MSI-X Capability Structure 82
- VF Device ID Register 96
- Page Size Registers 96
- Lane Error Status Register 98
- Bits Register Description 99
- Default Value 99
- Altera Corporation 100
- Registers 100
- Send Feedback 100
- Virtual Function Registers 102
- Name Description 103
- Reset and Clocks 107
- Hard IP for PCI Express 108
- Example Design 108
- UG-01097_sriov 109
- 2014.12.15 109
- Function Level Reset (FLR) 111
- Clock Domains 111
- Clock Summary 114
- Interrupts 115
- Error Handling 118
- Physical Layer Errors 119
- Data Link Layer Errors 119
- Transaction Layer Errors 120
- Error Type Description 121
- Status Bit Conditions 123
- IP Core Architecture 125
- Top-Level Interfaces 126
- Clocks and Reset 126
- Transceiver Reconfiguration 126
- Data Link Layer 127
- Physical Layer 129
- TX Packets 130
- Design Implementation 136
- CONF_DONE 137
- Endpoint Reset 137
- Root Port Reset 137
- SDC Timing Constraints 138
- Debugging 143
- Setting Up Simulation 146
- Use Third-Party PCIe Analyzer 148
- BIOS Enumeration Issues 148
- Address[31:2] 149
- Figure A-6: I/O Read Request 151
- Additional Information 155
- Typographic Conventions 156
- Visual Cue Meaning 157
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