Altera Stratix V Avalon-ST Manual do Utilizador Página 8
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Example Designs
Altera provides example designs to familiarize you with the available functionality. Each design connects
the device under test (DUT) to an application programming platform (APP), labeled APPs in the figure
below. Certain critical parameters of the APPs component are set to match the values of the DUT. If you
change these parameters, you must change the APPs component to match. You can change the values for
all other parameters of the DUT without editing the APPs component.
In this example design, the following parameters must be set to match the values set in the DUT:
• Targeted Device Family
• Lanes
• Lane Rate
• Application Clock Rate
• Port type
• Application Interface
• Tags supported
• Maximum payload size
• Total PFs
• Total VFs
The following Qsys example designs are available for the Stratix V Hard IP for PCI Express with SR-IOV.
You can download them from the <install_dir>/ ip/altera/altera_pcie/altera_pcie_sriov/example_design/
directory:
• sriov_top_dma_gen2_x8_128b.qsys
• sriov_top_dma_gen2_x8_256b.qsys
• sriov_top_dma_gen3_x8_256b.qsys
• sriov_top_target_gen2_x8_256b_2pf.qsys
• sriov_top_target_gen3_x8_256b_1pf_32vf.qsys
• sriov_top_target_gen3_x8_256b_2pf_128vf.qsys
• sriov_top_target_gen3_x8_256b_2pf_4vf.qsys
• sriov_top_target_gen3_x8_256b_1pf_4vf_avmm.qsys
Related Information
Getting Started with the SR-IOV DMA Example Design on page 2-1
Debug Features
Debug features allow observation and control of the Hard IP for faster debugging of system-level
problems.
Related Information
Debugging on page 12-1
UG-01097_sriov
2014.12.15
Example Designs
1-7
Datasheet
Altera Corporation
Send Feedback
- User Guide 1
- Datasheet 2
- Features 3
- Interface 4
- Release Information 7
- Device Family Support 7
- Example Designs 8
- Debug Features 8
- IP Core Verification 9
- Recommended Speed Grades 10
- Related Information 11
- Subscribe 12
- Qsys Subsystem Description 13
- Parameter Value 15
- Directory Description 16
- Parameter Settings 21
- Parameter Value Description 22
- SR-IOV System Settings 24
- Interrupt Capabilities 27
- Device Capabilities 29
- Error Reporting 30
- Link Capabilities 31
- Slot Capabilities 32
- Power Management 33
- PHY Characteristics 34
- Simulation Options 35
- Avalon-ST TX Interface 37
- Signal Direction Description 38
- Avalon‑ST RX Interface 40
- BAR Hit Signals 43
- Completion Side Band Signals 45
- Signal Directi 46
- Description 46
- Clock Signals 48
- Interrupt Interface 49
- Implementing MSI-X Interrupts 55
- LMI Signals 57
- Serial Data Signals 65
- Test Signals 70
- PIPE Interface Signals 71
- Byte Address 77
- MSI Registers 80
- MSI-X Capability Structure 82
- VF Device ID Register 96
- Page Size Registers 96
- Lane Error Status Register 98
- Bits Register Description 99
- Default Value 99
- Altera Corporation 100
- Registers 100
- Send Feedback 100
- Virtual Function Registers 102
- Name Description 103
- Reset and Clocks 107
- Hard IP for PCI Express 108
- Example Design 108
- UG-01097_sriov 109
- 2014.12.15 109
- Function Level Reset (FLR) 111
- Clock Domains 111
- Clock Summary 114
- Interrupts 115
- Error Handling 118
- Physical Layer Errors 119
- Data Link Layer Errors 119
- Transaction Layer Errors 120
- Error Type Description 121
- Status Bit Conditions 123
- IP Core Architecture 125
- Top-Level Interfaces 126
- Clocks and Reset 126
- Transceiver Reconfiguration 126
- Data Link Layer 127
- Physical Layer 129
- TX Packets 130
- Design Implementation 136
- CONF_DONE 137
- Endpoint Reset 137
- Root Port Reset 137
- SDC Timing Constraints 138
- Debugging 143
- Setting Up Simulation 146
- Use Third-Party PCIe Analyzer 148
- BIOS Enumeration Issues 148
- Address[31:2] 149
- Figure A-6: I/O Read Request 151
- Additional Information 155
- Typographic Conventions 156
- Visual Cue Meaning 157
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