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BAR Logic Details
The BAR block includes the following functions:
• Compares the addresses of received memory transactions to the BAR settings for the targeted function
• Generates the BAR hit signals and the function number associated with this transaction
• Discards all memory transactions that are not in the address range of any of the configured BARs
• Generates Unsupported Request (UR) Completions for requests that fail the BAR check
Local Management Interface (LMI)
SR-IOV LMI logic accesses Configuration Space Registers of all Physical and Virtual Functions. The LMI
logic accepts read and write requests from the Application Layer and directs requests to either the LMI
interface of the Hard IP or the Configuration Registers in the Configuration Block.
Related Information
LMI Signals on page 4-22
Physical and Virtual Function Address Assignments
The SR-IOV Bridge implements the PCI and PCI Express Configuration Spaces for two Physical
Functions (PFs) and 128 Virtual Functions (VFs) in soft logic. Altera SR-IOV bridge assigns function
numbers for PFs and VFs based on based on the following system attributes:
• Number of PFs.
• Availability of ARI support. (ARI support is required when the total number of PFs and VFs is greater
than eight.)
The following rules apply when specifying VFs:
• All systems that include VFs must include a minimum of four VFs.
• For systems without ARI support, the Application Layer logic can configure VFs in any manner
between PF0 and PF1.
• For system without ARI, the total maximum VF is either 6 for one PF and 7 for two PFs.
• For system with ARI, the maximum number of VFs is 128.
• Systems with ARI support must specify VFs in multiples if four.
Table 9-2: Function Address Map: One PF and No ARI
Function Number Assignments Function Type
0 Physical Function 0
1 Virtual Function 0 (required)
2 Virtual Function 1 (required)
3
Virtual Function 2 (required)
4
Virtual Function 3 (required)
5
Virtual Function 4 (optional)
UG-01097_sriov
2014.12.15
Physical and Virtual Function Address Assignments
9-9
IP Core Architecture
Altera Corporation
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- User Guide 1
- Datasheet 2
- Features 3
- Interface 4
- Release Information 7
- Device Family Support 7
- Example Designs 8
- Debug Features 8
- IP Core Verification 9
- Recommended Speed Grades 10
- Related Information 11
- Subscribe 12
- Qsys Subsystem Description 13
- Parameter Value 15
- Directory Description 16
- Parameter Settings 21
- Parameter Value Description 22
- SR-IOV System Settings 24
- Interrupt Capabilities 27
- Device Capabilities 29
- Error Reporting 30
- Link Capabilities 31
- Slot Capabilities 32
- Power Management 33
- PHY Characteristics 34
- Simulation Options 35
- Avalon-ST TX Interface 37
- Signal Direction Description 38
- Avalon‑ST RX Interface 40
- BAR Hit Signals 43
- Completion Side Band Signals 45
- Signal Directi 46
- Description 46
- Clock Signals 48
- Interrupt Interface 49
- Implementing MSI-X Interrupts 55
- LMI Signals 57
- Serial Data Signals 65
- Test Signals 70
- PIPE Interface Signals 71
- Byte Address 77
- MSI Registers 80
- MSI-X Capability Structure 82
- VF Device ID Register 96
- Page Size Registers 96
- Lane Error Status Register 98
- Bits Register Description 99
- Default Value 99
- Altera Corporation 100
- Registers 100
- Send Feedback 100
- Virtual Function Registers 102
- Name Description 103
- Reset and Clocks 107
- Hard IP for PCI Express 108
- Example Design 108
- UG-01097_sriov 109
- 2014.12.15 109
- Function Level Reset (FLR) 111
- Clock Domains 111
- Clock Summary 114
- Interrupts 115
- Error Handling 118
- Physical Layer Errors 119
- Data Link Layer Errors 119
- Transaction Layer Errors 120
- Error Type Description 121
- Status Bit Conditions 123
- IP Core Architecture 125
- Top-Level Interfaces 126
- Clocks and Reset 126
- Transceiver Reconfiguration 126
- Data Link Layer 127
- Physical Layer 129
- TX Packets 130
- Design Implementation 136
- CONF_DONE 137
- Endpoint Reset 137
- Root Port Reset 137
- SDC Timing Constraints 138
- Debugging 143
- Setting Up Simulation 146
- Use Third-Party PCIe Analyzer 148
- BIOS Enumeration Issues 148
- Address[31:2] 149
- Figure A-6: I/O Read Request 151
- Additional Information 155
- Typographic Conventions 156
- Visual Cue Meaning 157
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