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1. A rising edge on app_intx_req indicates the assertion of the corresponding legacy interrupt from the
client.
2. In response, the PF drives Assert_INTx to activate a legacy interrupt.
3. A falling edge on app_int_sts_x indicates the deassertion of the corresponding legacy interrupt from
the client.
4. In response, the PF sends Deassert_INTx to deactivate the legacy interrupt.
The Interrupt Pin register specifies the interrupt input used to signal interrupts. The PFs may be
configured with separate interrupt pins. Or, both PFs may share a common interrupt pin. You configure
the Interrupt Pin register in Qsys.
The Interrupt Line register specifies the interrupt controller (IRQ0–IRQ15) input of the in the Root
Port activated by each Assert_INTx message. You configure the Interrupt Line register in Qsys.
Table 5-3: Interrupt Line and Interrupt Pin Register -0x03C
Bit Location Description Default Value Access
[15:11] Not implemented 0 RO
[10:8] Interrupt Pin register. When legacy interrupts are enabled,
specifies the pin this function uses to signal an interrupt . The
following encodings are defined:
• 3'b001: INTA_IN
• 3'b010: INTB_IN
• 3'b011: INTC_IN
• 3'b100: INTD_IN
Specify in Qsys RO
[7:0] Interrupt Line register. Identifies the interrupt controller IRQx
input of the Root Port that is activated by this function’s
interrupt. The following encodings are defined:
• 6'h000000: IRQ0
• 6'h000001: IRQ1
• 6'h000002: IRQ2
• ...
• 6'h0000FF: unknown or not connected
Specify in Qsys RO
Related Information
PCI Local Bus Specification 3.0
UG-01097_sriov
2014.12.15
Interrupt Line and Interrupt Pin Register
5-5
Registers
Altera Corporation
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- User Guide 1
- Datasheet 2
- Features 3
- Interface 4
- Release Information 7
- Device Family Support 7
- Example Designs 8
- Debug Features 8
- IP Core Verification 9
- Recommended Speed Grades 10
- Related Information 11
- Subscribe 12
- Qsys Subsystem Description 13
- Parameter Value 15
- Directory Description 16
- Parameter Settings 21
- Parameter Value Description 22
- SR-IOV System Settings 24
- Interrupt Capabilities 27
- Device Capabilities 29
- Error Reporting 30
- Link Capabilities 31
- Slot Capabilities 32
- Power Management 33
- PHY Characteristics 34
- Simulation Options 35
- Avalon-ST TX Interface 37
- Signal Direction Description 38
- Avalon‑ST RX Interface 40
- BAR Hit Signals 43
- Completion Side Band Signals 45
- Signal Directi 46
- Description 46
- Clock Signals 48
- Interrupt Interface 49
- Implementing MSI-X Interrupts 55
- LMI Signals 57
- Serial Data Signals 65
- Test Signals 70
- PIPE Interface Signals 71
- Byte Address 77
- MSI Registers 80
- MSI-X Capability Structure 82
- VF Device ID Register 96
- Page Size Registers 96
- Lane Error Status Register 98
- Bits Register Description 99
- Default Value 99
- Altera Corporation 100
- Registers 100
- Send Feedback 100
- Virtual Function Registers 102
- Name Description 103
- Reset and Clocks 107
- Hard IP for PCI Express 108
- Example Design 108
- UG-01097_sriov 109
- 2014.12.15 109
- Function Level Reset (FLR) 111
- Clock Domains 111
- Clock Summary 114
- Interrupts 115
- Error Handling 118
- Physical Layer Errors 119
- Data Link Layer Errors 119
- Transaction Layer Errors 120
- Error Type Description 121
- Status Bit Conditions 123
- IP Core Architecture 125
- Top-Level Interfaces 126
- Clocks and Reset 126
- Transceiver Reconfiguration 126
- Data Link Layer 127
- Physical Layer 129
- TX Packets 130
- Design Implementation 136
- CONF_DONE 137
- Endpoint Reset 137
- Root Port Reset 137
- SDC Timing Constraints 138
- Debugging 143
- Setting Up Simulation 146
- Use Third-Party PCIe Analyzer 148
- BIOS Enumeration Issues 148
- Address[31:2] 149
- Figure A-6: I/O Read Request 151
- Additional Information 155
- Typographic Conventions 156
- Visual Cue Meaning 157
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