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Signal Direction Description
reset_status
Output Active high reset status signal. When asserted, this signal
indicates that the Hard IP clock is in reset. The reset_status
signal is synchronous to the pld_clk clock and is deasserted only
when the npor is deasserted and the Hard IP for PCI Express is
not in reset (reset_status_hip = 0). You should use reset_
status to drive the reset of your Application Layer. It resets the
Hard IP at power-up, for hot reset and link down events.
serdes_pll_locked
Output When asserted, indicates that the PLL that generates the
coreclkout_hip clock signal is locked. In pipe simulation mode
this signal is always asserted.
testin_zero
Output
When asserted, indicates accelerated initialization for simulation
is active.
Table 4-14: Status and Link Training Signals
The following table describes additional signals related to the reset function for the including the
ltsssm_state[4:0] bus that indicates the current link training state. These signals are not top-level signals of the
Stratix V Hard IP for PCI Express IP Core with SR-IOV. They are listed here to assist in debugging link training
issues.
Signal Direction Description
cfg_par_err
Output Indicates that a parity error in a TLP routed to the internal
Configuration Space. This error is also logged in the Vendor
Specific Extended Capability internal error register. You must
reset the Hard IP if this error occurs.
derr_cor_ext_rcv Output Indicates a corrected error in the RX buffer. This signal is for
debug only. It is not valid until the RX buffer is filled with data.
This is a pulse, not a level, signal. Internally, the pulse is
generated with the 500 MHz clock. A pulse extender extends the
signal so that the FPGA fabric running at 250 MHz can capture
it. Because the error was corrected by the IP core, no Application
Layer intervention is required.
derr_cor_ext_rpl Output Indicates a corrected ECC error in the retry buffer. This signal is
for debug only. Because the error was corrected by the IP core,
no Application Layer intervention is required.
derr_rpl Output Indicates an uncorrectable error in the retry buffer. This signal is
for debug only.
1
(4)
Debug signals are not rigorously verified and should only be used to observe behavior. Debug signals
should not be used to drive logic custom logic.
4-26
Reset, Status, and Link Training Signals
UG-01097_sriov
2014.12.15
Altera Corporation
Interfaces and Signal Descriptions
Send Feedback
- User Guide 1
- Datasheet 2
- Features 3
- Interface 4
- Release Information 7
- Device Family Support 7
- Example Designs 8
- Debug Features 8
- IP Core Verification 9
- Recommended Speed Grades 10
- Related Information 11
- Subscribe 12
- Qsys Subsystem Description 13
- Parameter Value 15
- Directory Description 16
- Parameter Settings 21
- Parameter Value Description 22
- SR-IOV System Settings 24
- Interrupt Capabilities 27
- Device Capabilities 29
- Error Reporting 30
- Link Capabilities 31
- Slot Capabilities 32
- Power Management 33
- PHY Characteristics 34
- Simulation Options 35
- Avalon-ST TX Interface 37
- Signal Direction Description 38
- Avalon‑ST RX Interface 40
- BAR Hit Signals 43
- Completion Side Band Signals 45
- Signal Directi 46
- Description 46
- Clock Signals 48
- Interrupt Interface 49
- Implementing MSI-X Interrupts 55
- LMI Signals 57
- Serial Data Signals 65
- Test Signals 70
- PIPE Interface Signals 71
- Byte Address 77
- MSI Registers 80
- MSI-X Capability Structure 82
- VF Device ID Register 96
- Page Size Registers 96
- Lane Error Status Register 98
- Bits Register Description 99
- Default Value 99
- Altera Corporation 100
- Registers 100
- Send Feedback 100
- Virtual Function Registers 102
- Name Description 103
- Reset and Clocks 107
- Hard IP for PCI Express 108
- Example Design 108
- UG-01097_sriov 109
- 2014.12.15 109
- Function Level Reset (FLR) 111
- Clock Domains 111
- Clock Summary 114
- Interrupts 115
- Error Handling 118
- Physical Layer Errors 119
- Data Link Layer Errors 119
- Transaction Layer Errors 120
- Error Type Description 121
- Status Bit Conditions 123
- IP Core Architecture 125
- Top-Level Interfaces 126
- Clocks and Reset 126
- Transceiver Reconfiguration 126
- Data Link Layer 127
- Physical Layer 129
- TX Packets 130
- Design Implementation 136
- CONF_DONE 137
- Endpoint Reset 137
- Root Port Reset 137
- SDC Timing Constraints 138
- Debugging 143
- Setting Up Simulation 146
- Use Third-Party PCIe Analyzer 148
- BIOS Enumeration Issues 148
- Address[31:2] 149
- Figure A-6: I/O Read Request 151
- Additional Information 155
- Typographic Conventions 156
- Visual Cue Meaning 157
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