Altera JESD204B IP Manual do Utilizador Página 92
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Figure 5-3: TX Path Assembler Block Diagram
Tail Bits
Padding
Assembling Multiplexing
TX Control
jesd204_tx_link_datain[(L*32)-1:0]
Configuration Register Settings
jesd204_tx_link_early_ready
jesd204_tx_link_data_valid
jesd204_tx_link_error
txframe_clk
txframe_rst_n
txlink_clk
txlink_rst_n
Control Unit
JESD204B IP Core
Data Link Layer
Data
Bus
Data
Bus
Data
Bus
Data
Bus
jesd204_tx_datain
[DATA_BUS_WIDTH-1:0]
(1)
JESD204B Transport Layer TX Block
Interface with
Avalon-ST
jesd204_tx_data_valid
jesd204_tx_data_ready
Interfaces with JESD204 IP Core
Data Link Layer and Control Unit
Parameter L, M, F, N, N’,S,
F1_FRAMECLK_DIV,
F2_FRAMECLK_DIV
Note:
1. The DATA_BUS_WIDTH value is the data input bus width size, which depends on the F and L parameter.
bus_width=M*S*N
F=(M*S*N_PRIME)/(8*L)
M*S=(8*F*L)/N_PRIME
bus_width=(8*F*L*N)/N_PRIME
• Tail bits padding block—pads incoming data (jesd204_tx_datain) with "0" if N < 16, so that the
padded data is 16 bits per sample.
• Assembling block—arranges the resulting data bits in a specific way according to the mapping scheme
(refer to Figure 5-2).
• Multiplexing block—sends the multiplexed data to the DLL interface, determined by certain control
signals from the TX control block.
Table 5-4: Assembler Parameter Settings
Parameter Description Value
L Number of lanes per converter device. 1–8
F Number of octets per frame. 1, 2, 4, 8
CS Number of control bits or conversion sample. 0–3
N Number of conversion bits per converter. 12-16
N' Number of transmitted bits per sample in the user data format. 16
UG-01142
2015.05.04
TX Path
5-11
JESD204B IP Core Design Guidelines
Altera Corporation
Send Feedback
- JESD204B IP Core User Guide 1
- Contents 2
- Item Description 4
- Datapath Modes 8
- IP Core Variation 8
- Run-Time Configuration 9
- Channel Bonding 10
- About the JESD204B IP Core 13
- Getting Started 15
- Upgrading IP Cores 16
- IP Core Status Description 17
- Design Walkthrough 20
- Programming an FPGA Device 25
- Pin Assignments 26
- JESD204B IP Core Parameters 30
- Parameter Value Description 31
- JESD204B IP Core Testbench 35
- Configuration Preset Value 36
- Testbench Simulation Flow 37
- Subscribe 38
- Frame Clock 39
- Transmitter 41
- TX Data Link Layer 42
- Configura‐ 43
- Description 43
- MSB 6 5 4 3 2 1 LSB 43
- User Data Phase 44
- Receiver 45
- RX Data Link Layer 46
- Frame Alignment 47
- Lane Alignment 47
- ILAS Data 48
- Initial Lane Synchronization 48
- RX PHY Layer 49
- Operation 50
- Scrambler/Descrambler 51
- SYNC_N Signal 51
- Link Reinitialization 53
- Link Startup Sequence 54
- Device Clock 57
- Link Clock 58
- Local Multi-Frame Clock 59
- Clock Correlation 60
- Reset Scheme 61
- Reset Sequence 62
- Registers 80
- Access Type Definition 81
- Design Example Components 84
- PLL Reconfiguration 85
- Operation Avalon-MM 86
- Interface Signal 86
- Byte Address 86
- Offset (6bits) 86
- Bit Value 86
- Transceiver Reset Controller 87
- Pattern Generator 87
- Pattern Checker 88
- Transport Layer 89
- F Parameter f 90
- (txframe_clk frequency) f 90
- (rxframe_clk frequency) 90
- TX Path Data Remapping 100
- Altera Corporation 100
- Send Feedback 100
- UG-01142 104
- 2015.05.04 104
- F FRAMECLK_DIV TX Latency 105
- Parameter Description Value 106
- Related Information 113
- RX Path Data Remapping 114
- Serial Port Interface (SPI) 117
- Control Unit 118
- Memory Block (ROM) 119
- Finite State Machine (FSM) 120
- System Parameters 121
- Run-Time Reconfiguration 124
- System Interface Signals 125
- Signal Clock 128
- Direction Description 128
- PHY (Stratix V and Arria V) 133
- Implementation Guidelines 139
- Programmable RBD Offset 140
- Programmable LMFC Offset 143
- K K K K K RK K K K K 146
- D D D DK D D 146
- DK D DK K K 146
- Clocking Scheme 148
- JESD204B Parameters 148
- SPI Programming 149
- Additional Information 155
- Date Version Changes 156
- How to Contact Altera 157
- Contact Method Address 158
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