Altera JESD204B IP Manual do Utilizador Página 9
- Página / 158
- Índice
- MARCADORES
Avaliado. / 5. Com base em avaliações de clientes
JESD204B IP Core Configuration
Table 2-1: JESD204B IP Core Configuration
Symbol Description Value
L Number of lanes per converter device 1-8
M Number of converters per device 1-256
F Number of octets per frame 1, 2, 4-256
S Number of transmitted samples per converter per frame 1-32
N Number of conversion bits per converter 1-32
N' Number of transmitted bits per sample (JESD204 word size,
which is in nibble group)
1-32
K Number of frames per multiframe 17/F ≤ K ≤ 32 ; 1-32
CS Number of control bits per conversion sample 0-3
CF Number of control words per frame clock period per link 0-32
HD High Density user data format 0 or 1
LMFC Local multiframe clock (F × K /4) link clock counts
(1)
Run-Time Configuration
The JESD204B IP core allows run-time configuration of LMF parameters.
The most critical parameters that must be set correctly during IP generation are the L and F parameters.
Parameter L denotes the maximum lanes supported while parameter F denotes the size of the deskew
buffer needed for deterministic latency. The hardware generates during parameterization, which means
that run-time programmability can only fall back from the parameterized and generated hardware, but
not beyond the parameterized IP core.
You can use run-time configuration for prototyping or evaluating the performance of converter devices
with various LMF configurations. However, in actual production,Altera recommends that you generate
the JESD204B IP core with the intended LMF to get an optimized gate count.
For example, if a converter device supports LMF = 442 and LMF = 222, to check the performance for both
configurations, you need to generate the JESD204B IP core with maximum F and L, which is L = 4 and F
= 2. During operation, you can use the fall back configuration to disable the lanes that are not used in
LMF = 222 mode. You must ensure that other JESD204B configurations like M, N, S, CS, CF, and HD do
not violate the parameter F setting. You can access the Configuration and Status Register (CSR) space to
modify other configurations such as:
• K (multi-frame)
• device and lane IDs
• enable or disable scrambler
• enable or disable character replacement
(1)
The value of F x K must be divisible by 4.
2-4
JESD204B IP Core Configuration
UG-01142
2015.05.04
Altera Corporation
About the JESD204B IP Core
Send Feedback
- JESD204B IP Core User Guide 1
- Contents 2
- Item Description 4
- Datapath Modes 8
- IP Core Variation 8
- Run-Time Configuration 9
- Channel Bonding 10
- About the JESD204B IP Core 13
- Getting Started 15
- Upgrading IP Cores 16
- IP Core Status Description 17
- Design Walkthrough 20
- Programming an FPGA Device 25
- Pin Assignments 26
- JESD204B IP Core Parameters 30
- Parameter Value Description 31
- JESD204B IP Core Testbench 35
- Configuration Preset Value 36
- Testbench Simulation Flow 37
- Subscribe 38
- Frame Clock 39
- Transmitter 41
- TX Data Link Layer 42
- Configura‐ 43
- Description 43
- MSB 6 5 4 3 2 1 LSB 43
- User Data Phase 44
- Receiver 45
- RX Data Link Layer 46
- Frame Alignment 47
- Lane Alignment 47
- ILAS Data 48
- Initial Lane Synchronization 48
- RX PHY Layer 49
- Operation 50
- Scrambler/Descrambler 51
- SYNC_N Signal 51
- Link Reinitialization 53
- Link Startup Sequence 54
- Device Clock 57
- Link Clock 58
- Local Multi-Frame Clock 59
- Clock Correlation 60
- Reset Scheme 61
- Reset Sequence 62
- Registers 80
- Access Type Definition 81
- Design Example Components 84
- PLL Reconfiguration 85
- Operation Avalon-MM 86
- Interface Signal 86
- Byte Address 86
- Offset (6bits) 86
- Bit Value 86
- Transceiver Reset Controller 87
- Pattern Generator 87
- Pattern Checker 88
- Transport Layer 89
- F Parameter f 90
- (txframe_clk frequency) f 90
- (rxframe_clk frequency) 90
- TX Path Data Remapping 100
- Altera Corporation 100
- Send Feedback 100
- UG-01142 104
- 2015.05.04 104
- F FRAMECLK_DIV TX Latency 105
- Parameter Description Value 106
- Related Information 113
- RX Path Data Remapping 114
- Serial Port Interface (SPI) 117
- Control Unit 118
- Memory Block (ROM) 119
- Finite State Machine (FSM) 120
- System Parameters 121
- Run-Time Reconfiguration 124
- System Interface Signals 125
- Signal Clock 128
- Direction Description 128
- PHY (Stratix V and Arria V) 133
- Implementation Guidelines 139
- Programmable RBD Offset 140
- Programmable LMFC Offset 143
- K K K K K RK K K K K 146
- D D D DK D D 146
- DK D DK K K 146
- Clocking Scheme 148
- JESD204B Parameters 148
- SPI Programming 149
- Additional Information 155
- Date Version Changes 156
- How to Contact Altera 157
- Contact Method Address 158
Manuais e produtos relacionados com Instrumentos de medida Altera JESD204B IP
Instrumentos de medida Altera Nios II Embedded Evaluation Kit Cyclone III Editio Manual do Utilizador
(3 páginas)
(3 páginas)
Instrumentos de medida Altera Nios II Embedded Evaluation Kit Cyclone III Editio Manual do Utilizador
(80 páginas)
(80 páginas)
Instrumentos de medida Altera Phase-Locked Loop Reconfiguration IP Core Manual do Utilizador
(51 páginas)
(51 páginas)
Instrumentos de medida Altera Serial Digital Interface (SDI) MegaCore Function Manual do Utilizador
(140 páginas)
(140 páginas)
Instrumentos de medida Altera 100G Development Kit, Stratix V GX Edition Manual do Utilizador
(44 páginas)
(44 páginas)
Instrumentos de medida Altera Stratix V Avalon-MM Interface for PCIe Solutions Manual do Utilizador
(184 páginas)
(184 páginas)
Instrumentos de medida Altera 10-Gbps Ethernet MAC MegaCore Function Manual do Utilizador
(175 páginas)
(175 páginas)
© 2020, manymanuals-pt.com. Todos os direitos reservados. | 0.092 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Comentários a estes Manuais