Altera JESD204B IP Manual do Utilizador Página 138
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To run the Tcl script using the Quartus II sofware, follow these steps:
1. Launch the Quartus II software.
2. On the View menu, click Utility Windows and select Tcl Console.
3.
In the Tcl Console, type cd <example_design_directory>/ed_synth to go to the
specified directory.
4.
Type source gen_quartus_synth.tcl to generate the JESD204B design example for compila‐
tion.
To run the Tcl script using the command line, follow these steps:
1. Obtain the Quartus II software resource.
2.
Type cd <example_design_directory>/ed_synth to go to the specified directory.
3.
Type quartus_sh -t gen_ed_quartus_synth.tcl to generate the JESD204B design
example for compilation.
Compiling the JESD204B IP Core Design Example
You can use the generated .qip file to include relevant files into your project. Generate the Quartus II
synthesis compilation files by running the script (gen_quartus_synth.tcl) located in the
<example_design_directory>/ed_synth/ directory.
Note: If you use the Quartus II Tcl console to generate the gen_quartus_synth.tcl script, close all Quartus
II project before you start generating.
To compile your design using the Quartus II software , follow these steps:
1. Launch the Quartus II software.
2. On the File menu, click Open Project > Select <example_design_directory>/ed_synth/example_design/.
3. Select jesd204b_ed.qpf.
(38)
4. On the Processing menu, click Start Compilation.
At the end of the compilation, the Quartus II software provides a pass/fail indication.
(38)
This is the default quartus project file that the Quartus II software automatically generates. You can edit this
file and the .qsf file according to your design preference.
UG-01142
2015.05.04
Compiling the JESD204B IP Core Design Example
5-57
JESD204B IP Core Design Guidelines
Altera Corporation
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- JESD204B IP Core User Guide 1
- Contents 2
- Item Description 4
- Datapath Modes 8
- IP Core Variation 8
- Run-Time Configuration 9
- Channel Bonding 10
- About the JESD204B IP Core 13
- Getting Started 15
- Upgrading IP Cores 16
- IP Core Status Description 17
- Design Walkthrough 20
- Programming an FPGA Device 25
- Pin Assignments 26
- JESD204B IP Core Parameters 30
- Parameter Value Description 31
- JESD204B IP Core Testbench 35
- Configuration Preset Value 36
- Testbench Simulation Flow 37
- Subscribe 38
- Frame Clock 39
- Transmitter 41
- TX Data Link Layer 42
- Configura‐ 43
- Description 43
- MSB 6 5 4 3 2 1 LSB 43
- User Data Phase 44
- Receiver 45
- RX Data Link Layer 46
- Frame Alignment 47
- Lane Alignment 47
- ILAS Data 48
- Initial Lane Synchronization 48
- RX PHY Layer 49
- Operation 50
- Scrambler/Descrambler 51
- SYNC_N Signal 51
- Link Reinitialization 53
- Link Startup Sequence 54
- Device Clock 57
- Link Clock 58
- Local Multi-Frame Clock 59
- Clock Correlation 60
- Reset Scheme 61
- Reset Sequence 62
- Registers 80
- Access Type Definition 81
- Design Example Components 84
- PLL Reconfiguration 85
- Operation Avalon-MM 86
- Interface Signal 86
- Byte Address 86
- Offset (6bits) 86
- Bit Value 86
- Transceiver Reset Controller 87
- Pattern Generator 87
- Pattern Checker 88
- Transport Layer 89
- F Parameter f 90
- (txframe_clk frequency) f 90
- (rxframe_clk frequency) 90
- TX Path Data Remapping 100
- Altera Corporation 100
- Send Feedback 100
- UG-01142 104
- 2015.05.04 104
- F FRAMECLK_DIV TX Latency 105
- Parameter Description Value 106
- Related Information 113
- RX Path Data Remapping 114
- Serial Port Interface (SPI) 117
- Control Unit 118
- Memory Block (ROM) 119
- Finite State Machine (FSM) 120
- System Parameters 121
- Run-Time Reconfiguration 124
- System Interface Signals 125
- Signal Clock 128
- Direction Description 128
- PHY (Stratix V and Arria V) 133
- Implementation Guidelines 139
- Programmable RBD Offset 140
- Programmable LMFC Offset 143
- K K K K K RK K K K K 146
- D D D DK D D 146
- DK D DK K K 146
- Clocking Scheme 148
- JESD204B Parameters 148
- SPI Programming 149
- Additional Information 155
- Date Version Changes 156
- How to Contact Altera 157
- Contact Method Address 158
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