Altera JESD204B IP Manual do Utilizador Página 126
- Página / 158
- Índice
- MARCADORES
Avaliado. / 5. Com base em avaliações de clientes
Signal Clock
Domain
Direction Description
rx_sysref[LINK-1:0] link_clk
Input RX SYSREF signal for JESD204B Subclass 1
implementation.
tx_dev_sync_n[LINK-
1:0]
link_clk
Output Indicates a clean synchronization request at the TX
path. This is an active low signal and is asserted 0 to
indicate a synchronization request. The SYNC_N
signal error reporting is masked out of this signal.
This signal is also asserted during software-initiated
synchronization.
dev_lane_
aligned[LINK-1:0]
link_clk
Output Indicates that all lanes for this device are aligned at
the RX path.
rx_dev_sync_n[LINK-
1:0]
link_clk
Output Indicates a SYNC_N to the transmitter. This is an
active low signal and is asserted 0 to indicate a
synchronization request. Instead of reporting the link
error through this signal, the JESD204B IP core uses
the jesd204_rx_int signal to indicate an interrupt.
Signal Clock
Domain
Direction Description
SPI
miso sclk
Input Output data from a slave to the input of the master.
mosi sclk
Output Output data from the master to the inputs of the
slaves.
sclk mgmt_clk
Output Clock driven by the master to slaves, to synchronize
the data bits.
ss_n[2:0] sclk
Output Active low select signal driven by the master to
individual slaves, to select the target slave. Defaults to
3 bits.
Signal Clock
Domain
Direction Description
Serial Data and Control
rx_serial_
data[LINK*L-1:0]
— Input Differential high speed serial input data. The clock is
recovered from the serial data stream.
tx_serial_
data[LINK*L-1:0]
device_
clk
Output Differential high speed serial output data. The clock
is embedded in the serial data stream.
UG-01142
2015.05.04
System Interface Signals
5-45
JESD204B IP Core Design Guidelines
Altera Corporation
Send Feedback
- JESD204B IP Core User Guide 1
- Contents 2
- Item Description 4
- Datapath Modes 8
- IP Core Variation 8
- Run-Time Configuration 9
- Channel Bonding 10
- About the JESD204B IP Core 13
- Getting Started 15
- Upgrading IP Cores 16
- IP Core Status Description 17
- Design Walkthrough 20
- Programming an FPGA Device 25
- Pin Assignments 26
- JESD204B IP Core Parameters 30
- Parameter Value Description 31
- JESD204B IP Core Testbench 35
- Configuration Preset Value 36
- Testbench Simulation Flow 37
- Subscribe 38
- Frame Clock 39
- Transmitter 41
- TX Data Link Layer 42
- Configura‐ 43
- Description 43
- MSB 6 5 4 3 2 1 LSB 43
- User Data Phase 44
- Receiver 45
- RX Data Link Layer 46
- Frame Alignment 47
- Lane Alignment 47
- ILAS Data 48
- Initial Lane Synchronization 48
- RX PHY Layer 49
- Operation 50
- Scrambler/Descrambler 51
- SYNC_N Signal 51
- Link Reinitialization 53
- Link Startup Sequence 54
- Device Clock 57
- Link Clock 58
- Local Multi-Frame Clock 59
- Clock Correlation 60
- Reset Scheme 61
- Reset Sequence 62
- Registers 80
- Access Type Definition 81
- Design Example Components 84
- PLL Reconfiguration 85
- Operation Avalon-MM 86
- Interface Signal 86
- Byte Address 86
- Offset (6bits) 86
- Bit Value 86
- Transceiver Reset Controller 87
- Pattern Generator 87
- Pattern Checker 88
- Transport Layer 89
- F Parameter f 90
- (txframe_clk frequency) f 90
- (rxframe_clk frequency) 90
- TX Path Data Remapping 100
- Altera Corporation 100
- Send Feedback 100
- UG-01142 104
- 2015.05.04 104
- F FRAMECLK_DIV TX Latency 105
- Parameter Description Value 106
- Related Information 113
- RX Path Data Remapping 114
- Serial Port Interface (SPI) 117
- Control Unit 118
- Memory Block (ROM) 119
- Finite State Machine (FSM) 120
- System Parameters 121
- Run-Time Reconfiguration 124
- System Interface Signals 125
- Signal Clock 128
- Direction Description 128
- PHY (Stratix V and Arria V) 133
- Implementation Guidelines 139
- Programmable RBD Offset 140
- Programmable LMFC Offset 143
- K K K K K RK K K K K 146
- D D D DK D D 146
- DK D DK K K 146
- Clocking Scheme 148
- JESD204B Parameters 148
- SPI Programming 149
- Additional Information 155
- Date Version Changes 156
- How to Contact Altera 157
- Contact Method Address 158
Manuais e produtos relacionados com Instrumentos de medida Altera JESD204B IP
Instrumentos de medida Altera Nios II Embedded Evaluation Kit Cyclone III Editio Manual do Utilizador
(3 páginas)
(3 páginas)
Instrumentos de medida Altera Nios II Embedded Evaluation Kit Cyclone III Editio Manual do Utilizador
(80 páginas)
(80 páginas)
Instrumentos de medida Altera Phase-Locked Loop Reconfiguration IP Core Manual do Utilizador
(51 páginas)
(51 páginas)
Instrumentos de medida Altera Serial Digital Interface (SDI) MegaCore Function Manual do Utilizador
(140 páginas)
(140 páginas)
Instrumentos de medida Altera 100G Development Kit, Stratix V GX Edition Manual do Utilizador
(44 páginas)
(44 páginas)
Instrumentos de medida Altera Stratix V Avalon-MM Interface for PCIe Solutions Manual do Utilizador
(184 páginas)
(184 páginas)
Instrumentos de medida Altera 10-Gbps Ethernet MAC MegaCore Function Manual do Utilizador
(175 páginas)
(175 páginas)
© 2020, manymanuals-pt.com. Todos os direitos reservados. | 0.052 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Comentários a estes Manuais