Altera JESD204B IP Manual do Utilizador Página 14
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Device Family Data Path Number of
Lanes
ALMs ALUTs Logic
Registers
Memory Block
(M10K/M20K)
(6)
(7)
Arria 10
RX
1 1043 1504 1194 0
2 1575 2265 1815 0
4 2828 3927 3060 0
8 5356 7347 5546 0
TX
1 695 1092 931 0
2 878 1373 1049 0
4 1240 1888 1285 0
8 1908 2969 1757 0
Stratix V
RX
1 1056 1542 1215 0
2 1642 2363 1857 0
4 2936 4097 3140 0
8 5546 7697 5712 0
TX
1 719 1150 948 0
2 937 1488 1083 0
4 1358 2114 1353 0
8 2137 3417 1894 0
Related Information
• JESD204B IP Core Parameters on page 3-16
• Fitter Resources Reports in the Quartus II Help
Information about the Quartus II resource utilization reporting, including ALMs needed.
(6)
M10K for Arria V device, M20K for Arria V GZ, Stratix V and Arria 10 devices.
(7)
The Quartus II software may auto-fit to use MLAB when the memory size is too small. Conversion from
MLAB to M20K or M10K was performed for the numbers listed above.
(7)
The Quartus II software may auto-fit to use MLAB when the memory size is too small. Conversion from
MLAB to M20K or M10K was performed for the numbers listed above.
UG-01142
2015.05.04
Performance and Resource Utilization
2-9
About the JESD204B IP Core
Altera Corporation
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- JESD204B IP Core User Guide 1
- Contents 2
- Item Description 4
- Datapath Modes 8
- IP Core Variation 8
- Run-Time Configuration 9
- Channel Bonding 10
- About the JESD204B IP Core 13
- Getting Started 15
- Upgrading IP Cores 16
- IP Core Status Description 17
- Design Walkthrough 20
- Programming an FPGA Device 25
- Pin Assignments 26
- JESD204B IP Core Parameters 30
- Parameter Value Description 31
- JESD204B IP Core Testbench 35
- Configuration Preset Value 36
- Testbench Simulation Flow 37
- Subscribe 38
- Frame Clock 39
- Transmitter 41
- TX Data Link Layer 42
- Configura‐ 43
- Description 43
- MSB 6 5 4 3 2 1 LSB 43
- User Data Phase 44
- Receiver 45
- RX Data Link Layer 46
- Frame Alignment 47
- Lane Alignment 47
- ILAS Data 48
- Initial Lane Synchronization 48
- RX PHY Layer 49
- Operation 50
- Scrambler/Descrambler 51
- SYNC_N Signal 51
- Link Reinitialization 53
- Link Startup Sequence 54
- Device Clock 57
- Link Clock 58
- Local Multi-Frame Clock 59
- Clock Correlation 60
- Reset Scheme 61
- Reset Sequence 62
- Registers 80
- Access Type Definition 81
- Design Example Components 84
- PLL Reconfiguration 85
- Operation Avalon-MM 86
- Interface Signal 86
- Byte Address 86
- Offset (6bits) 86
- Bit Value 86
- Transceiver Reset Controller 87
- Pattern Generator 87
- Pattern Checker 88
- Transport Layer 89
- F Parameter f 90
- (txframe_clk frequency) f 90
- (rxframe_clk frequency) 90
- TX Path Data Remapping 100
- Altera Corporation 100
- Send Feedback 100
- UG-01142 104
- 2015.05.04 104
- F FRAMECLK_DIV TX Latency 105
- Parameter Description Value 106
- Related Information 113
- RX Path Data Remapping 114
- Serial Port Interface (SPI) 117
- Control Unit 118
- Memory Block (ROM) 119
- Finite State Machine (FSM) 120
- System Parameters 121
- Run-Time Reconfiguration 124
- System Interface Signals 125
- Signal Clock 128
- Direction Description 128
- PHY (Stratix V and Arria V) 133
- Implementation Guidelines 139
- Programmable RBD Offset 140
- Programmable LMFC Offset 143
- K K K K K RK K K K K 146
- D D D DK D D 146
- DK D DK K K 146
- Clocking Scheme 148
- JESD204B Parameters 148
- SPI Programming 149
- Additional Information 155
- Date Version Changes 156
- How to Contact Altera 157
- Contact Method Address 158
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