Altera JESD204B IP Manual do Utilizador Página 108
- Página / 158
- Índice
- MARCADORES
Avaliado. / 5. Com base em avaliações de clientes
Signal Clock Domain Direction Description
Between Avalon- ST and Transport Layer
jesd204_rx_
dataout[(OUTPUT_BUS_
WIDTH)-1:0]
rxframe_clk
Output
RX data to the Avalon-ST source interface. The
transport layer arranges the data in a specific
order, as illustrated in the cases listed in RX Path
Data Remapping section.
jesd204_rx_
controlout[CONTROL_
BUS_WIDTH -1:0]
rxframe_clk Output RX control data to the Avalon-ST source
interface. The transport layer arranges the data in
a specific order, as illustrated in the cases listed in
RX Path Data Remapping section.
jesd204_rx_data_
valid
rxframe_clk
Output
Indicates whether the data from the transport
layer to the Avalon-ST sink interface is valid or
invalid.
• 0—data is invalid
• 1—data is valid
jesd204_rx_data_
ready
rxframe_clk Input
Indicates that the Avalon-ST sink interface is
ready to accept data from the transport layer.
• 0—Avalon-ST sink interface is not ready to
receive data
• 1—Avalon-ST sink interface is ready to receive
data
Signal Clock Domain Direction Description
Between Transport Layer and DLL
jesd204_rx_link_
datain[(L*32)-1:0]
rxlink_clk Input Indicates received data from the DLL to the
transport layer, where four octets are packed into
a 32-bit data width per lane. The data format is
big endian. The table below illustrates the data
mapping for L = 4:
jesd204_rx_link_datain [x:y] Lane
[31:0] 0
[63:32] 1
[95:64] 2
[127:96] 3
Connect this signal to the RX DLL jesd204_rx_
link_data[] output pin.
UG-01142
2015.05.04
RX Path
5-27
JESD204B IP Core Design Guidelines
Altera Corporation
Send Feedback
- JESD204B IP Core User Guide 1
- Contents 2
- Item Description 4
- Datapath Modes 8
- IP Core Variation 8
- Run-Time Configuration 9
- Channel Bonding 10
- About the JESD204B IP Core 13
- Getting Started 15
- Upgrading IP Cores 16
- IP Core Status Description 17
- Design Walkthrough 20
- Programming an FPGA Device 25
- Pin Assignments 26
- JESD204B IP Core Parameters 30
- Parameter Value Description 31
- JESD204B IP Core Testbench 35
- Configuration Preset Value 36
- Testbench Simulation Flow 37
- Subscribe 38
- Frame Clock 39
- Transmitter 41
- TX Data Link Layer 42
- Configura‐ 43
- Description 43
- MSB 6 5 4 3 2 1 LSB 43
- User Data Phase 44
- Receiver 45
- RX Data Link Layer 46
- Frame Alignment 47
- Lane Alignment 47
- ILAS Data 48
- Initial Lane Synchronization 48
- RX PHY Layer 49
- Operation 50
- Scrambler/Descrambler 51
- SYNC_N Signal 51
- Link Reinitialization 53
- Link Startup Sequence 54
- Device Clock 57
- Link Clock 58
- Local Multi-Frame Clock 59
- Clock Correlation 60
- Reset Scheme 61
- Reset Sequence 62
- Registers 80
- Access Type Definition 81
- Design Example Components 84
- PLL Reconfiguration 85
- Operation Avalon-MM 86
- Interface Signal 86
- Byte Address 86
- Offset (6bits) 86
- Bit Value 86
- Transceiver Reset Controller 87
- Pattern Generator 87
- Pattern Checker 88
- Transport Layer 89
- F Parameter f 90
- (txframe_clk frequency) f 90
- (rxframe_clk frequency) 90
- TX Path Data Remapping 100
- Altera Corporation 100
- Send Feedback 100
- UG-01142 104
- 2015.05.04 104
- F FRAMECLK_DIV TX Latency 105
- Parameter Description Value 106
- Related Information 113
- RX Path Data Remapping 114
- Serial Port Interface (SPI) 117
- Control Unit 118
- Memory Block (ROM) 119
- Finite State Machine (FSM) 120
- System Parameters 121
- Run-Time Reconfiguration 124
- System Interface Signals 125
- Signal Clock 128
- Direction Description 128
- PHY (Stratix V and Arria V) 133
- Implementation Guidelines 139
- Programmable RBD Offset 140
- Programmable LMFC Offset 143
- K K K K K RK K K K K 146
- D D D DK D D 146
- DK D DK K K 146
- Clocking Scheme 148
- JESD204B Parameters 148
- SPI Programming 149
- Additional Information 155
- Date Version Changes 156
- How to Contact Altera 157
- Contact Method Address 158
Manuais e produtos relacionados com Instrumentos de medida Altera JESD204B IP
Instrumentos de medida Altera Nios II Embedded Evaluation Kit Cyclone III Editio Manual do Utilizador
(3 páginas)
(3 páginas)
Instrumentos de medida Altera Nios II Embedded Evaluation Kit Cyclone III Editio Manual do Utilizador
(80 páginas)
(80 páginas)
Instrumentos de medida Altera Phase-Locked Loop Reconfiguration IP Core Manual do Utilizador
(51 páginas)
(51 páginas)
Instrumentos de medida Altera Serial Digital Interface (SDI) MegaCore Function Manual do Utilizador
(140 páginas)
(140 páginas)
Instrumentos de medida Altera 100G Development Kit, Stratix V GX Edition Manual do Utilizador
(44 páginas)
(44 páginas)
Instrumentos de medida Altera Stratix V Avalon-MM Interface for PCIe Solutions Manual do Utilizador
(184 páginas)
(184 páginas)
Instrumentos de medida Altera 10-Gbps Ethernet MAC MegaCore Function Manual do Utilizador
(175 páginas)
(175 páginas)
© 2020, manymanuals-pt.com. Todos os direitos reservados. | 0.062 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Comentários a estes Manuais