Altera JESD204B IP Manual do Utilizador descarregar pdf (Página 54)

There are two modes of entry for link reinitialization:

• Hardware initiated link reinitialization:

• For TX, the reception of SYNC_N for more than five frames and nine octets triggers link reinitializa‐

tion.

• For RX, the loss of code group synchronization, frame alignment and lane alignment errors cause

the IP core to assert SYNC_N and request for link reinitialization.

• Software initiated link reinitialization—both the TX and RX IP core allow software to request for link

reinitialization.

• For TX, the IP core transmits /K/ character and wait for the receiver to assert SYNC_N to indicate

that it has entered CS_INIT state.

• For RX, the IP core asserts SYNC_N to request for link reinitialization.

Hardware initiated link reinitialization can be globally disabled through the csr_link_reinit_disable

Hardware initiated link reinitialization can be issued as interrupt depending on the error type and

interrupt error enable. If lane misalignment has been detected as a result of a phase change in local timing

reference, the software can rely on this interrupt trigger to initiates a LMFC realignment. The realignment

process occurs by first resampling SYSREF and then issuing a link reinitialization request.

Link Startup Sequence

Set the run-time LMF configuration when the txlink_rst_n or rxlink_rst_n signals are asserted. Upon

txlink_rst_n or rxlink_rst_n deassertion, the JESD204B IP core begins operation. The following

sections describe the detailed operation for each subclass mode.

TX (Subclass 0)

Upon reset deassertion, the JESD204B TX IP core is in CGS phase. SYNC_N deassertion from the converter

device enables the JESD204B TX IP core to exit CGS phase and enter ILAS phase (if csr_lane_sync_en =

1) or User Data phase (if csr_lane_sync_en = 0).

TX (Subclass 1)

Upon reset deassertion, the JESD204B TX IP core is in CGS phase. SYNC_N deassertion from the converter

device enables the JESD204B TX IP core to exit CGS phase. The IP core ensures that at least one SYSREF

rising edge is sampled before exiting CGS phase and entering ILAS phase. This is to prevent a race

condition where the SYNC_N is deasserted before SYSREF is sampled. SYSREF sampling is crucial to ensure

deterministic latency in the JESD204B Subclass 1 system.

TX (Subclass 2)

Similar to Subclass 1 mode, the JESD204B TX IP core is in CGS phase upon reset deassertion. The LMFC

alignment between the converter and IP core starts after SYNC_N deassertion. The JESD204B TX IP core

detects the deassertion of SYNC_N and compares the timing to its own LMFC. The required adjustment in

the link clock domain is updated in the register map. You need to update the final phase adjustment value

in the registers for it to transfer the value to the converter during the ILAS phase. The DAC adjusts the

LMFC phase and acknowledge the phase change with an error report. This error report contains the new

DAC LMFC phase information, which allows the loop to iterate until the phase between them is aligned.

UG-01142

2015.05.04

Link Startup Sequence

4-17

JESD204B IP Core Functional Description

Altera Corporation

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