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Avalon-MM Interface
The Avalon-MM slave interface provides access to internal CSRs. The read and write data width is 32-bits
(DWORD access). The Avalon-MM slave is asynchronous to the txlink_clk, txframe_clk, rxlink_clk,
and rxframe_clk clock domains. You are recommended to release the reset for the CSR configuration
space first. All run-time JESD204B configurations like L, F, M, N, N', CS, CF, and HD should be set before
releasing the reset for link and frame clock domain.
Each write transfer has a writeWaitTime of 0 cycle while a read transfer has a readWaitTime of 1 cycle and
readLatency of 1 cycle.
Related Information
Avalon Interface Specification
More information about the Avalon-ST and Avalon-MM interfaces, including timing diagrams.
Transmitter
The transmitter block, which interfaces to DAC devices, takes one of more digital sample streams and
converts them into one or more serial streams.
The transmitter performs the following functions:
• Data scrambling
• Frame or lane alignment
• Character generation
• Serial lane monitoring
• 8B/10B encoding
• Data serializer
Figure 4-3: Transmitter Data Path Block Diagram
TX Frame
Deassembly
Per Device
TX CSR
Per Device
TX CTL
Per Device
Scrambler
Data Link
Layer (TX)
Soft
PCS
(TX)
Hard PCS
and
Transceiver
JESD204B
(TX) Per Device
CSR
CSR
CSR
32 Bit PCS
Per Channel
Transceiver (TX)
Per Device
SYNC_N
SYSREF
TX_INT
TXLINK_CLKTXFRAME_CLK
Avalon-MM
Avalon-ST
To Avalon
Interface
Bus
JESD204 TX Transport Layer with
Base and Transceiver Design Example
Avalon-ST
32 Bits per Channel
Serial Interface
(TX_n, TX_p)
The transmitter block consists of the following modules:
4-4
Transmitter
UG-01142
2015.05.04
Altera Corporation
JESD204B IP Core Functional Description
Send Feedback
- JESD204B IP Core User Guide 1
- Contents 2
- Item Description 4
- Datapath Modes 8
- IP Core Variation 8
- Run-Time Configuration 9
- Channel Bonding 10
- About the JESD204B IP Core 13
- Getting Started 15
- Upgrading IP Cores 16
- IP Core Status Description 17
- Design Walkthrough 20
- Programming an FPGA Device 25
- Pin Assignments 26
- JESD204B IP Core Parameters 30
- Parameter Value Description 31
- JESD204B IP Core Testbench 35
- Configuration Preset Value 36
- Testbench Simulation Flow 37
- Subscribe 38
- Frame Clock 39
- Transmitter 41
- TX Data Link Layer 42
- Configura‐ 43
- Description 43
- MSB 6 5 4 3 2 1 LSB 43
- User Data Phase 44
- Receiver 45
- RX Data Link Layer 46
- Frame Alignment 47
- Lane Alignment 47
- ILAS Data 48
- Initial Lane Synchronization 48
- RX PHY Layer 49
- Operation 50
- Scrambler/Descrambler 51
- SYNC_N Signal 51
- Link Reinitialization 53
- Link Startup Sequence 54
- Device Clock 57
- Link Clock 58
- Local Multi-Frame Clock 59
- Clock Correlation 60
- Reset Scheme 61
- Reset Sequence 62
- Registers 80
- Access Type Definition 81
- Design Example Components 84
- PLL Reconfiguration 85
- Operation Avalon-MM 86
- Interface Signal 86
- Byte Address 86
- Offset (6bits) 86
- Bit Value 86
- Transceiver Reset Controller 87
- Pattern Generator 87
- Pattern Checker 88
- Transport Layer 89
- F Parameter f 90
- (txframe_clk frequency) f 90
- (rxframe_clk frequency) 90
- TX Path Data Remapping 100
- Altera Corporation 100
- Send Feedback 100
- UG-01142 104
- 2015.05.04 104
- F FRAMECLK_DIV TX Latency 105
- Parameter Description Value 106
- Related Information 113
- RX Path Data Remapping 114
- Serial Port Interface (SPI) 117
- Control Unit 118
- Memory Block (ROM) 119
- Finite State Machine (FSM) 120
- System Parameters 121
- Run-Time Reconfiguration 124
- System Interface Signals 125
- Signal Clock 128
- Direction Description 128
- PHY (Stratix V and Arria V) 133
- Implementation Guidelines 139
- Programmable RBD Offset 140
- Programmable LMFC Offset 143
- K K K K K RK K K K K 146
- D D D DK D D 146
- DK D DK K K 146
- Clocking Scheme 148
- JESD204B Parameters 148
- SPI Programming 149
- Additional Information 155
- Date Version Changes 156
- How to Contact Altera 157
- Contact Method Address 158
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