Altera JESD204B IP Manual do Utilizador Página 70
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Signal Width Direction Description
sync_n
1 Input Indicates SYNC_N from the converter device or
receiver. This is an active low signal and is
asserted 0 to indicate a synchronization
request or error reporting from the converter
device.
To indicate a synchronization request, the
converter device must assert this signal for at
least five frames and nine octets.
To indicate an error reporting, the converter
device must ensure that the pulse is at least
one cycle of the txlink_clk signal or two
cycles of the txframe_clk signal (whichever
period is longer).
dev_sync_n
1 Output Indicates a clean synchronization request. This
is an active low signal and is asserted 0 to
indicate a synchronization request only. The
sync_n signal error reporting is being masked
out of this signal. This signal is also asserted
during software-initiated synchronization.
mdev_sync_n
1 Input Indicates a multidevice synchronization
request. Synchronize signal combination
should be done externally and then input to
the JESD204B IP core through this signal.
• For subclass 0—combine the dev_sync_n
signal from all multipoint links before
connecting to the mdev_sync_n signal.
• For subclass 1—connect the dev_sync_n
signal to the mdev_sync_n signal for each
link respectively.
In a single link instance where multidevice
synchronization is not needed, tie the dev_
sync_n signal to this signal.
Signal Width Direction Description
CSR
jesd204_tx_frame_
error
1 Input Optional signal to indicate an empty data
stream due to invalid data. This signal is
asserted high to indicate an error during data
transfer from the transport layer to the TX
core.
UG-01142
2015.05.04
Transmitter
4-33
JESD204B IP Core Functional Description
Altera Corporation
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- JESD204B IP Core User Guide 1
- Contents 2
- Item Description 4
- Datapath Modes 8
- IP Core Variation 8
- Run-Time Configuration 9
- Channel Bonding 10
- About the JESD204B IP Core 13
- Getting Started 15
- Upgrading IP Cores 16
- IP Core Status Description 17
- Design Walkthrough 20
- Programming an FPGA Device 25
- Pin Assignments 26
- JESD204B IP Core Parameters 30
- Parameter Value Description 31
- JESD204B IP Core Testbench 35
- Configuration Preset Value 36
- Testbench Simulation Flow 37
- Subscribe 38
- Frame Clock 39
- Transmitter 41
- TX Data Link Layer 42
- Configura‐ 43
- Description 43
- MSB 6 5 4 3 2 1 LSB 43
- User Data Phase 44
- Receiver 45
- RX Data Link Layer 46
- Frame Alignment 47
- Lane Alignment 47
- ILAS Data 48
- Initial Lane Synchronization 48
- RX PHY Layer 49
- Operation 50
- Scrambler/Descrambler 51
- SYNC_N Signal 51
- Link Reinitialization 53
- Link Startup Sequence 54
- Device Clock 57
- Link Clock 58
- Local Multi-Frame Clock 59
- Clock Correlation 60
- Reset Scheme 61
- Reset Sequence 62
- Registers 80
- Access Type Definition 81
- Design Example Components 84
- PLL Reconfiguration 85
- Operation Avalon-MM 86
- Interface Signal 86
- Byte Address 86
- Offset (6bits) 86
- Bit Value 86
- Transceiver Reset Controller 87
- Pattern Generator 87
- Pattern Checker 88
- Transport Layer 89
- F Parameter f 90
- (txframe_clk frequency) f 90
- (rxframe_clk frequency) 90
- TX Path Data Remapping 100
- Altera Corporation 100
- Send Feedback 100
- UG-01142 104
- 2015.05.04 104
- F FRAMECLK_DIV TX Latency 105
- Parameter Description Value 106
- Related Information 113
- RX Path Data Remapping 114
- Serial Port Interface (SPI) 117
- Control Unit 118
- Memory Block (ROM) 119
- Finite State Machine (FSM) 120
- System Parameters 121
- Run-Time Reconfiguration 124
- System Interface Signals 125
- Signal Clock 128
- Direction Description 128
- PHY (Stratix V and Arria V) 133
- Implementation Guidelines 139
- Programmable RBD Offset 140
- Programmable LMFC Offset 143
- K K K K K RK K K K K 146
- D D D DK D D 146
- DK D DK K K 146
- Clocking Scheme 148
- JESD204B Parameters 148
- SPI Programming 149
- Additional Information 155
- Date Version Changes 156
- How to Contact Altera 157
- Contact Method Address 158
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