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Control Register Access (CRA) Avalon-MM Slave Port
Table 5-19: Configuration Space Register Descriptions
The optional CRA Avalon-MM slave port provides host access to selected Configuration Space and status
registers. These registers are read only. For registers that are less than 32 bits, the upper bits are unused.
Byte Offset
Register Dir Description
14'h0000 cfg_dev_ctrl[15:0]
O cfg_devctrl[15:0] is device control for the PCI
Express capability structure.
14'h0004 cfg_dev_ctrl2[15:0]
O cfg_dev2ctrl[15:0] is device control 2 for the
PCI Express capability structure.
14'h0008 cfg_link_ctrl[15:0]
O cfg_link_ctrl[15:0]is the primary Link Control
of the PCI Express capability structure.
For Gen2 or Gen3 operation, you must write a 1’b1
to Retrain Link bit (Bit[5] of the cfg_link_ctrl) of
the Root Port to initiate retraining to a higher data
rate after the initial link training to Gen1 L0 state.
Retraining directs the LTSSM to the Recovery state.
Retraining to a higher data rate is not automatic
even if both devices on the link are capable of a
higher data rate.
14'h000C cfg_link_ctrl2[15:0]
O cfg_link_ctrl2[31:16] is the secondary Link
Control register of the PCI Express capability
structure for Gen2 operation.
When tl_cfg_addr=2, tl_cfg_ctl returns the
primary and secondary Link Control registers,
{cfg_link_ctrl[15:0], cfg_link_
ctrl2[15:0]}, the primary Link Status register
contents is available on tl_cfg_sts[46:31].
For Gen1 variants, the link bandwidth notification
bit is always set to 0.For Gen2 variants, this bit is set
to 1.
14'h0010 cfg_prm_cmd[15:0]
O Base/Primary Command register for the PCI
Configuration Space.
14'h0014 cfg_root_ctrl[7:0]
O Root control and status register of the PCI-Express
capability. This register is only available in Root
Port mode.
5-26
Control Register Access (CRA) Avalon-MM Slave Port
UG-01154
2014.12.18
Altera Corporation
Registers
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- User Guide 1
- Features 3
- Interface 5
- Release Information 8
- Example Designs 9
- Debug Features 9
- IP Core Verification 9
- Related Information 10
- Altera Corporation 11
- Datasheet 11
- Send Feedback 11
- Parameter Value 17
- Directory Description 18
- Time TLP Type Payload 18
- TLP Header 18
- Creating a Quartus II Project 19
- Compiling the Design 20
- Parameter Settings 22
- Parameter Value Description 23
- Device Capabilities 28
- Error Reporting 28
- Link Capabilities 29
- MSI and MSI-X Capabilities 29
- Power Management 30
- PCIe Address Space Settings 31
- RX Master Module 36
- TX Slave Module 38
- Signal Name Directio 39
- Description 39
- Bits Name Description 41
- Clock Signals 45
- Signal Direction Description 46
- MSI Interrupts for Endpoints 51
- Serial Data Signals 53
- 9 Ch 18 Ch 54
- PIPE Interface Signals 64
- Test Signals 68
- Registers 70
- Altera-Defined VSEC Registers 77
- CvP Registers 78
- Bits Register Description 82
- Register Access Description 86
- Read DMA Example 91
- Byte Offset 95
- Register Dir Description 95
- Reset and Clocks 100
- Example Design 101
- Hard IP for PCI Express 101
- UG-01154 102
- 2014.12.18 102
- Clock Domains 104
- Data Rate Frequency 105
- Clock Summary 106
- Error Handling 107
- Physical Layer Errors 108
- Data Link Layer Errors 108
- Transaction Layer Errors 109
- Error Type Description 110
- Status Bit Conditions 112
- IP Core Architecture 114
- Hard IP for PCI Express 115
- Top-Level Interfaces 116
- Avalon-MM DMA Interface 116
- Clocks and Reset 116
- Transceiver Reconfiguration 116
- Interrupts 116
- Data Link Layer 117
- Physical Layer 119
- TX Packets 120
- Altera FPGA 122
- Qsys System 123
- Subscribe 125
- Address[31:2] 130
- Figure A-6: I/O Read Request 132
- Additional Information 136
- Date Version Changes Made 137
- How to Contact Altera 139
- Typographic Conventions 140
- Visual Cue Meaning 141
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