Altera V-Series Avalon-MM DMA Manual do Utilizador Página 72
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Byte Address Hard IP Configuration Space Register Corresponding Section in PCIe Specification
0x008 Class Code, Revision ID Type 0 Configuration Space Header
Type 1 Configuration Space Header
The Type 1 Configuration Space is not
available for the Avalon-MM with DMA
interface
0x00C BIST, Header Type, Primary Latency Timer,
Cache Line Size
Type 0 Configuration Space Header
Type 1 Configuration Space Header
The Type 1 Configuration Space is not
available for the Avalon-MM with DMA
interface
0x010 Base Address 0 Base Address Registers
0x014 Base Address 1 Base Address Registers
0x018 Base Address 2
Secondary Latency Timer, Subordinate Bus
Number, Secondary Bus Number, Primary
Bus Number
Base Address Registers
Secondary Latency Timer, Type 1
Configuration Space Header, Primary
Bus Number
0x01C Base Address 3
Secondary Status, I/O Limit, I/O Base
Base Address Registers
Secondary Status Register ,Type 1
Configuration Space Header
0x020 Base Address 4
Memory Limit, Memory Base
Base Address Registers
Type 1 Configuration Space Header
0x024 Base Address 5
Prefetchable Memory Limit, Prefetchable
Memory Base
Base Address Registers
Prefetchable Memory Limit, Prefetchable
Memory Base
0x028 Reserved
Prefetchable Base Upper 32 Bits
N/A
Type 1 Configuration Space Header
0x02C Subsystem ID, Subsystem Vendor ID
Prefetchable Limit Upper 32 Bits
Type 0 Configuration Space Header
Type 1 Configuration Space Header
0x030 I/O Limit Upper 16 Bits, I/O Base Upper 16
Bits
Type 0 Configuration Space Header
Type 1 Configuration Space Header
UG-01154
2014.12.18
Correspondence between Configuration Space Registers and the PCIe Specification
5-3
Registers
Altera Corporation
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- User Guide 1
- Features 3
- Interface 5
- Release Information 8
- Example Designs 9
- Debug Features 9
- IP Core Verification 9
- Related Information 10
- Altera Corporation 11
- Datasheet 11
- Send Feedback 11
- Parameter Value 17
- Directory Description 18
- Time TLP Type Payload 18
- TLP Header 18
- Creating a Quartus II Project 19
- Compiling the Design 20
- Parameter Settings 22
- Parameter Value Description 23
- Device Capabilities 28
- Error Reporting 28
- Link Capabilities 29
- MSI and MSI-X Capabilities 29
- Power Management 30
- PCIe Address Space Settings 31
- RX Master Module 36
- TX Slave Module 38
- Signal Name Directio 39
- Description 39
- Bits Name Description 41
- Clock Signals 45
- Signal Direction Description 46
- MSI Interrupts for Endpoints 51
- Serial Data Signals 53
- 9 Ch 18 Ch 54
- PIPE Interface Signals 64
- Test Signals 68
- Registers 70
- Altera-Defined VSEC Registers 77
- CvP Registers 78
- Bits Register Description 82
- Register Access Description 86
- Read DMA Example 91
- Byte Offset 95
- Register Dir Description 95
- Reset and Clocks 100
- Example Design 101
- Hard IP for PCI Express 101
- UG-01154 102
- 2014.12.18 102
- Clock Domains 104
- Data Rate Frequency 105
- Clock Summary 106
- Error Handling 107
- Physical Layer Errors 108
- Data Link Layer Errors 108
- Transaction Layer Errors 109
- Error Type Description 110
- Status Bit Conditions 112
- IP Core Architecture 114
- Hard IP for PCI Express 115
- Top-Level Interfaces 116
- Avalon-MM DMA Interface 116
- Clocks and Reset 116
- Transceiver Reconfiguration 116
- Interrupts 116
- Data Link Layer 117
- Physical Layer 119
- TX Packets 120
- Altera FPGA 122
- Qsys System 123
- Subscribe 125
- Address[31:2] 130
- Figure A-6: I/O Read Request 132
- Additional Information 136
- Date Version Changes Made 137
- How to Contact Altera 139
- Typographic Conventions 140
- Visual Cue Meaning 141
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