Altera V-Series Avalon-MM DMA Manual do Utilizador Página 28
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Device Capabilities
Table 3-4: Capabilities Registers
Parameter Possible Values Default Value Description
Maximum
payload size
128 bytes
256 bytes
128 bytes Specifies the maximum payload size supported. This
parameter sets the read-only value of the max payload
size supported field of the Device Capabilities register
(0x084[2:0]). Address: 0x084.
Implement
completion
timeout
disable
On/Off On For Endpoints using PCI Express version 2.1 or 3.0, this
option must be On. The timeout range is selectable.
When On, the core supports the completion timeout
disable mechanism via the PCI Express Device
Control Register 2. The Application Layer logic must
implement the actual completion timeout mechanism
for the required ranges.
Error Reporting
Table 3-5: Error Reporting
Parameter Value Default Value Description
Advanced
error
reporting
(AER)
On/Off Off When On, enables the Advanced Error Reporting (AER)
capability.
ECRC
checking
On/Off Off When On, enables ECRC checking. Sets the read-only
value of the ECRC check capable bit in the Advanced
Error Capabilities and Control Register. This
parameter requires you to enable the AER capability.
ECRC
generation
On/Off Off
When On, enables ECRC generation capability. Sets the
read-only value of the ECRC generation capable bit in
the Advanced Error Capabilities and Control
Register. This parameter requires you to enable the
AER capability.
Note:
1. Throughout this user guide, the terms word, dword and qword have the same meaning that they have
in the PCI Express Base Specification. A word is 16 bits, a dword is 32 bits, and a qword is 64 bits.
Related Information
PCI Express Base Specification Revision 2.1 or 3.0
UG-01154
2014.12.18
Device Capabilities
3-7
Parameter Settings
Altera Corporation
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- User Guide 1
- Features 3
- Interface 5
- Release Information 8
- Example Designs 9
- Debug Features 9
- IP Core Verification 9
- Related Information 10
- Altera Corporation 11
- Datasheet 11
- Send Feedback 11
- Parameter Value 17
- Directory Description 18
- Time TLP Type Payload 18
- TLP Header 18
- Creating a Quartus II Project 19
- Compiling the Design 20
- Parameter Settings 22
- Parameter Value Description 23
- Device Capabilities 28
- Error Reporting 28
- Link Capabilities 29
- MSI and MSI-X Capabilities 29
- Power Management 30
- PCIe Address Space Settings 31
- RX Master Module 36
- TX Slave Module 38
- Signal Name Directio 39
- Description 39
- Bits Name Description 41
- Clock Signals 45
- Signal Direction Description 46
- MSI Interrupts for Endpoints 51
- Serial Data Signals 53
- 9 Ch 18 Ch 54
- PIPE Interface Signals 64
- Test Signals 68
- Registers 70
- Altera-Defined VSEC Registers 77
- CvP Registers 78
- Bits Register Description 82
- Register Access Description 86
- Read DMA Example 91
- Byte Offset 95
- Register Dir Description 95
- Reset and Clocks 100
- Example Design 101
- Hard IP for PCI Express 101
- UG-01154 102
- 2014.12.18 102
- Clock Domains 104
- Data Rate Frequency 105
- Clock Summary 106
- Error Handling 107
- Physical Layer Errors 108
- Data Link Layer Errors 108
- Transaction Layer Errors 109
- Error Type Description 110
- Status Bit Conditions 112
- IP Core Architecture 114
- Hard IP for PCI Express 115
- Top-Level Interfaces 116
- Avalon-MM DMA Interface 116
- Clocks and Reset 116
- Transceiver Reconfiguration 116
- Interrupts 116
- Data Link Layer 117
- Physical Layer 119
- TX Packets 120
- Altera FPGA 122
- Qsys System 123
- Subscribe 125
- Address[31:2] 130
- Figure A-6: I/O Read Request 132
- Additional Information 136
- Date Version Changes Made 137
- How to Contact Altera 139
- Typographic Conventions 140
- Visual Cue Meaning 141
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