Altera V-Series Avalon-MM DMA Manual do Utilizador Página 138
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Date Version Changes Made
Made the following changes to the user guide:
• Removed 125 MHz clock as optional refclk frequency in V-
Series devices. V-Series devices support an 100 MHz reference
clock as specified by the PCI Express Base Specification, Rev 3.0
• Corrected values for Maximum payload size parameter. The sizes
available are 128 or 256 bytes.
• Enhanced definition of Device ID and Sub-system Vendor ID to
say that these registers are only valid in the Type 0 (Endpoint)
Configuration Space.
• Removed 125 MHz clock as optional refclk frequency in V-
Series devices. V-Series devices support an 100 MHz reference
clock as specified by the PCI Express Base Specification, Rev 3.0.
• Added Next Steps in Creating a Design for PCI Express to
Datasheet chapter.
• Removed the Transaction Layer Protocol Details chapter. This
information only applies to the Avalon-ST interface.
• Removed txdatavalid0 signal from the PIPE interface. This
signal is not available.
• Removed references to the MegaWizard
®
Plug-In Manager. In
14.0 the IP Parameter Editor Powered by Qsys has replaced the
MegaWizard Plug-In Manager.
• Added definitions for test_in[2], test_in[6] and test_in[7].
• Corrected interface widths in the Performance and Resource
Utilization V-Series Avalon-MM DMA for PCI Express table in the
Datasheet: V-Series Avalon-MM DMA for PCIe chapter.
• Removed discussion of pclk. This clock is not customer accessible
in Arria 10 devices.
• Corrected Reset Controller in V-Series Devices figure in Reset and
Clocks chapter.
• Corrected bit definitions for CvP Status register.
• Removed PLL from channel placement figures.
• Added fast passive parallel (FPP) to supported configuration
schemes in CvP in Arria 10 Devices figure.
• Updated Power Supply Voltage Requirements table.
UG-01154
2014.12.18
Revision History for the Avalon-MM Interface with DMA
B-3
Additional Information
Altera Corporation
Send Feedback
- User Guide 1
- Features 3
- Interface 5
- Release Information 8
- Example Designs 9
- Debug Features 9
- IP Core Verification 9
- Related Information 10
- Altera Corporation 11
- Datasheet 11
- Send Feedback 11
- Parameter Value 17
- Directory Description 18
- Time TLP Type Payload 18
- TLP Header 18
- Creating a Quartus II Project 19
- Compiling the Design 20
- Parameter Settings 22
- Parameter Value Description 23
- Device Capabilities 28
- Error Reporting 28
- Link Capabilities 29
- MSI and MSI-X Capabilities 29
- Power Management 30
- PCIe Address Space Settings 31
- RX Master Module 36
- TX Slave Module 38
- Signal Name Directio 39
- Description 39
- Bits Name Description 41
- Clock Signals 45
- Signal Direction Description 46
- MSI Interrupts for Endpoints 51
- Serial Data Signals 53
- 9 Ch 18 Ch 54
- PIPE Interface Signals 64
- Test Signals 68
- Registers 70
- Altera-Defined VSEC Registers 77
- CvP Registers 78
- Bits Register Description 82
- Register Access Description 86
- Read DMA Example 91
- Byte Offset 95
- Register Dir Description 95
- Reset and Clocks 100
- Example Design 101
- Hard IP for PCI Express 101
- UG-01154 102
- 2014.12.18 102
- Clock Domains 104
- Data Rate Frequency 105
- Clock Summary 106
- Error Handling 107
- Physical Layer Errors 108
- Data Link Layer Errors 108
- Transaction Layer Errors 109
- Error Type Description 110
- Status Bit Conditions 112
- IP Core Architecture 114
- Hard IP for PCI Express 115
- Top-Level Interfaces 116
- Avalon-MM DMA Interface 116
- Clocks and Reset 116
- Transceiver Reconfiguration 116
- Interrupts 116
- Data Link Layer 117
- Physical Layer 119
- TX Packets 120
- Altera FPGA 122
- Qsys System 123
- Subscribe 125
- Address[31:2] 130
- Figure A-6: I/O Read Request 132
- Additional Information 136
- Date Version Changes Made 137
- How to Contact Altera 139
- Typographic Conventions 140
- Visual Cue Meaning 141
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