Altera V-Series Avalon-MM DMA Manual do Utilizador Página 89
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Address
Offset
Register Access Description
0x010
C
EP Write Status and Descriptor
FIFO Base (High)
RW Specifies the upper 32 bits of the base
address of the write descriptor table in
Endpoint memory. The read DMA fetches
the table from Root Complex memory and
writes the table to this location. Software
must program this register before
programming the lower 32-bit register at
offset 0x108.
0x011
0
WR_DMA_LAST_PTR
RW When read, returns the ID of the last
descriptor requested. If no DMA request
is outstanding or the DMA is in reset,
returns a value 0xFF.
When written, specifies the ID of the last
descriptor requested. The difference
between the value read and the value
written is the number of descriptors to be
processed.
For example, if the value reads 4, the last
descriptor requested is 4. To specify 5
more descriptors, software should write a
9 into the RD_DMA_LAST_PTR register. The
DMA executes 5 more descriptors.
The Descriptor ID loops back to 0 after
reaching WR_TABLE_SIZE.
For example, if the WR_TABLE_SIZE value
read is 126 and you want to execute three
more descriptors, software must write 127,
and then 1 into the WR_DMA_LAST_PTR
register.
0x011
4
WR_TABLE_SIZE
RW
Specifies the size of the Read descriptor
table. Set to the number of descriptors - 1.
By default, WR_TABLE_SIZE is set to 127.
This value specifies the last Descriptor
ID.
0x011
8
WR_CONTROL
RW
[31:1] Reserved.
[0]Done. When set, the Descriptor
Controller writes the Done bit for each
descriptor in the status table. The
Descriptor Controller sends a single MSI
interrupt after the final descriptor
completes.
5-20
DMA Descriptor Controller Registers
UG-01154
2014.12.18
Altera Corporation
Registers
Send Feedback
- User Guide 1
- Features 3
- Interface 5
- Release Information 8
- Example Designs 9
- Debug Features 9
- IP Core Verification 9
- Related Information 10
- Altera Corporation 11
- Datasheet 11
- Send Feedback 11
- Parameter Value 17
- Directory Description 18
- Time TLP Type Payload 18
- TLP Header 18
- Creating a Quartus II Project 19
- Compiling the Design 20
- Parameter Settings 22
- Parameter Value Description 23
- Device Capabilities 28
- Error Reporting 28
- Link Capabilities 29
- MSI and MSI-X Capabilities 29
- Power Management 30
- PCIe Address Space Settings 31
- RX Master Module 36
- TX Slave Module 38
- Signal Name Directio 39
- Description 39
- Bits Name Description 41
- Clock Signals 45
- Signal Direction Description 46
- MSI Interrupts for Endpoints 51
- Serial Data Signals 53
- 9 Ch 18 Ch 54
- PIPE Interface Signals 64
- Test Signals 68
- Registers 70
- Altera-Defined VSEC Registers 77
- CvP Registers 78
- Bits Register Description 82
- Register Access Description 86
- Read DMA Example 91
- Byte Offset 95
- Register Dir Description 95
- Reset and Clocks 100
- Example Design 101
- Hard IP for PCI Express 101
- UG-01154 102
- 2014.12.18 102
- Clock Domains 104
- Data Rate Frequency 105
- Clock Summary 106
- Error Handling 107
- Physical Layer Errors 108
- Data Link Layer Errors 108
- Transaction Layer Errors 109
- Error Type Description 110
- Status Bit Conditions 112
- IP Core Architecture 114
- Hard IP for PCI Express 115
- Top-Level Interfaces 116
- Avalon-MM DMA Interface 116
- Clocks and Reset 116
- Transceiver Reconfiguration 116
- Interrupts 116
- Data Link Layer 117
- Physical Layer 119
- TX Packets 120
- Altera FPGA 122
- Qsys System 123
- Subscribe 125
- Address[31:2] 130
- Figure A-6: I/O Read Request 132
- Additional Information 136
- Date Version Changes Made 137
- How to Contact Altera 139
- Typographic Conventions 140
- Visual Cue Meaning 141
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