Altera V-Series Avalon-MM DMA Manual do Utilizador Página 88
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Address
Offset
Register Access Description
0x001
8
RD_CONTROL
RW
[31:1] Reserved.
[0]Done. When set, the Descriptor
Controller writes the Done bit for each
descriptor in the status table. The
Descriptor Controller sends a single MSI
interrupt after the final descriptor
completes.
Table 5-16: DMA Descriptor Controller Registers for Write DMAs
Address
Offset
Register Access Description
0x010
0
RC Write Status and Descriptor
Base (Low)
R/W Specifies the lower 32-bits of the base
address of the write status and descriptor
table in the Root Complex memory. This
address must be on a 32-byte boundary.
Software must program this register after
programming the upper 32-bit register at
offset 0x104.
0x010
4
RC Write Status and Descriptor
Base (High)
R/W Specifies the upper 32-bits of the base
address of the write status and descriptor
table in the Root Complex memory.
Software must program this register
before programming the lower 32-bit
register at offset 0x100.
0x010
8
EP Write Status and Descriptor
FIFO Base (Low)
RW Specifies the lower 32 bits of the base
address of the write descriptor table in
Endpoint memory. The Write Descriptor
Controller requests descriptors from Root
Complex memory and writes the descrip‐
tors to this location. The address is the
Avalon-MM address of the Descriptor
Controller's Write Descriptor Table
Avalon-MM Slave Port as seen by the
Read DMA Avalon-MM Master Port.
Software must program this register after
programming the upper 32-bit register at
offset 0x10C.
UG-01154
2014.12.18
DMA Descriptor Controller Registers
5-19
Registers
Altera Corporation
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- User Guide 1
- Features 3
- Interface 5
- Release Information 8
- Example Designs 9
- Debug Features 9
- IP Core Verification 9
- Related Information 10
- Altera Corporation 11
- Datasheet 11
- Send Feedback 11
- Parameter Value 17
- Directory Description 18
- Time TLP Type Payload 18
- TLP Header 18
- Creating a Quartus II Project 19
- Compiling the Design 20
- Parameter Settings 22
- Parameter Value Description 23
- Device Capabilities 28
- Error Reporting 28
- Link Capabilities 29
- MSI and MSI-X Capabilities 29
- Power Management 30
- PCIe Address Space Settings 31
- RX Master Module 36
- TX Slave Module 38
- Signal Name Directio 39
- Description 39
- Bits Name Description 41
- Clock Signals 45
- Signal Direction Description 46
- MSI Interrupts for Endpoints 51
- Serial Data Signals 53
- 9 Ch 18 Ch 54
- PIPE Interface Signals 64
- Test Signals 68
- Registers 70
- Altera-Defined VSEC Registers 77
- CvP Registers 78
- Bits Register Description 82
- Register Access Description 86
- Read DMA Example 91
- Byte Offset 95
- Register Dir Description 95
- Reset and Clocks 100
- Example Design 101
- Hard IP for PCI Express 101
- UG-01154 102
- 2014.12.18 102
- Clock Domains 104
- Data Rate Frequency 105
- Clock Summary 106
- Error Handling 107
- Physical Layer Errors 108
- Data Link Layer Errors 108
- Transaction Layer Errors 109
- Error Type Description 110
- Status Bit Conditions 112
- IP Core Architecture 114
- Hard IP for PCI Express 115
- Top-Level Interfaces 116
- Avalon-MM DMA Interface 116
- Clocks and Reset 116
- Transceiver Reconfiguration 116
- Interrupts 116
- Data Link Layer 117
- Physical Layer 119
- TX Packets 120
- Altera FPGA 122
- Qsys System 123
- Subscribe 125
- Address[31:2] 130
- Figure A-6: I/O Read Request 132
- Additional Information 136
- Date Version Changes Made 137
- How to Contact Altera 139
- Typographic Conventions 140
- Visual Cue Meaning 141
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