Altera V-Series Avalon-MM DMA Manual do Utilizador Página 38
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Figure 4-5: RXM Master Writes To Memory in the Avalon-MM Address Space
AvRxmAddress_<n>_o[63:0]
AvRxmWrite_<n>_o
AvRxmWriteData_<n>_o[31:0]
AvRxmByteEnable_<n>_o[3:0]
AvRxmWaitRequest_<n>_i
AvRxmRead_<n>_o
AvRxmReadDataValid_<n>_i
AvRxmReadData_<n>_i[31:0]
800041080
00001010 00000000 00000001 00003800 00000000
8000410C 80004110 80004114 80004118 80004100
128: for the bursting 128-bit Avalon-MM interface
TX Slave Module
The TX Slave module translates Avalon-MM master read and write requests to PCI Express TLPs for the
Root Port. The TX Slave Control module supports a single outstanding non-bursting request. It typically
sends status updates to the host. This is a 32-bit Avalon-MM slave bus.
Table 4-4: TX Slave Control
Signal Name Direction Description
TxsChipSelect_i
Input When asserted, indicates that this slave interface is selected.
TxsRead_i
Input When asserted, specifies an TX Avalon-MM slave read request
from the Root Complex or Root Port.
TxsWrite_i
Input When asserted, specifies an TX Avalon-MM slave write request
to the Root Complex or Root Port.
TxsWriteData_i[<w>-
1:0]
Input Specifies the Avalon-MM data for a write command.
TxsAddress_i[<w>-1:0]
Input Specifies the Avalon-MM byte address for the read or write
command. The width of this address bus is specified by the
parameter Address width of accessible PCIe memory space.
TxsByteEnable_i[3:0]
Input Specifies the valid bytes for a write command.
TxsReadData_o[<w>-
1:0]
Output Specifies the read completion data.
TxsReadDataValid_o
Output
When asserted, indicates that TxsReadData_o[31:0] is valid.
UG-01154
2014.12.18
TX Slave Module
4-7
Interfaces and Signal Descriptions
Altera Corporation
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- User Guide 1
- Features 3
- Interface 5
- Release Information 8
- Example Designs 9
- Debug Features 9
- IP Core Verification 9
- Related Information 10
- Altera Corporation 11
- Datasheet 11
- Send Feedback 11
- Parameter Value 17
- Directory Description 18
- Time TLP Type Payload 18
- TLP Header 18
- Creating a Quartus II Project 19
- Compiling the Design 20
- Parameter Settings 22
- Parameter Value Description 23
- Device Capabilities 28
- Error Reporting 28
- Link Capabilities 29
- MSI and MSI-X Capabilities 29
- Power Management 30
- PCIe Address Space Settings 31
- RX Master Module 36
- TX Slave Module 38
- Signal Name Directio 39
- Description 39
- Bits Name Description 41
- Clock Signals 45
- Signal Direction Description 46
- MSI Interrupts for Endpoints 51
- Serial Data Signals 53
- 9 Ch 18 Ch 54
- PIPE Interface Signals 64
- Test Signals 68
- Registers 70
- Altera-Defined VSEC Registers 77
- CvP Registers 78
- Bits Register Description 82
- Register Access Description 86
- Read DMA Example 91
- Byte Offset 95
- Register Dir Description 95
- Reset and Clocks 100
- Example Design 101
- Hard IP for PCI Express 101
- UG-01154 102
- 2014.12.18 102
- Clock Domains 104
- Data Rate Frequency 105
- Clock Summary 106
- Error Handling 107
- Physical Layer Errors 108
- Data Link Layer Errors 108
- Transaction Layer Errors 109
- Error Type Description 110
- Status Bit Conditions 112
- IP Core Architecture 114
- Hard IP for PCI Express 115
- Top-Level Interfaces 116
- Avalon-MM DMA Interface 116
- Clocks and Reset 116
- Transceiver Reconfiguration 116
- Interrupts 116
- Data Link Layer 117
- Physical Layer 119
- TX Packets 120
- Altera FPGA 122
- Qsys System 123
- Subscribe 125
- Address[31:2] 130
- Figure A-6: I/O Read Request 132
- Additional Information 136
- Date Version Changes Made 137
- How to Contact Altera 139
- Typographic Conventions 140
- Visual Cue Meaning 141
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