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Table 4-14: Read Descriptor Controller Avalon-MM Master Interface
Signal Name Direction Description
RdDTSAddress_i[7:0]
Input Specifies the descriptor address.
RdDTSBurstCount_
i[4:0] or [5:0]
Input Specifies the burst count in 128- or 256-bit words.
RdDTSChipSelect_i
Input When asserted, indicates that the read targets this slave port.
RdDTSWaitRequest_o
Output When asserted, indicates that the Avalon-MM slave device is not
ready to respond.
RdDTSWriteData_
i[255:0] or [127:0]
Input Drives the 128- or 256-bit write data.
RdDTSWrite_i
Input
When asserted, indicates a write transaction.
Write Descriptor Table Avalon-MM Slave Port
Table 4-15: Write Descriptor Controller Avalon-MM Master Interface
Host software writes descriptors to the Avalon-MM slave port of the descriptor table. This port connects to a
bursting DMA write master interface.
Signal Name Direction Description
WrDTSAddress_i[7:0]
Input Specifies the descriptor address for the write data.
WrDTSBurstCount_
i[4:0] or [5:0]
Input Specifies the burst count in 128- or 256-bit words.
WrDTSChipSelect_i
Input When asserted, indicates that the write is for this slave port.
WrDTSWaitRequest_o
Output When asserted, indicates that the Avalon-MM slave device is not
ready to respond.
WrDTSWriteData_
i[255:0] or [127:0]
Input Drives the 128- or 256-bit write data.
WrDTSWrite_i
Input
When asserted, indicates a write transaction.
UG-01154
2014.12.18
Write Descriptor Table Avalon-MM Slave Port
4-13
Interfaces and Signal Descriptions
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- User Guide 1
- Features 3
- Interface 5
- Release Information 8
- Example Designs 9
- Debug Features 9
- IP Core Verification 9
- Related Information 10
- Altera Corporation 11
- Datasheet 11
- Send Feedback 11
- Parameter Value 17
- Directory Description 18
- Time TLP Type Payload 18
- TLP Header 18
- Creating a Quartus II Project 19
- Compiling the Design 20
- Parameter Settings 22
- Parameter Value Description 23
- Device Capabilities 28
- Error Reporting 28
- Link Capabilities 29
- MSI and MSI-X Capabilities 29
- Power Management 30
- PCIe Address Space Settings 31
- RX Master Module 36
- TX Slave Module 38
- Signal Name Directio 39
- Description 39
- Bits Name Description 41
- Clock Signals 45
- Signal Direction Description 46
- MSI Interrupts for Endpoints 51
- Serial Data Signals 53
- 9 Ch 18 Ch 54
- PIPE Interface Signals 64
- Test Signals 68
- Registers 70
- Altera-Defined VSEC Registers 77
- CvP Registers 78
- Bits Register Description 82
- Register Access Description 86
- Read DMA Example 91
- Byte Offset 95
- Register Dir Description 95
- Reset and Clocks 100
- Example Design 101
- Hard IP for PCI Express 101
- UG-01154 102
- 2014.12.18 102
- Clock Domains 104
- Data Rate Frequency 105
- Clock Summary 106
- Error Handling 107
- Physical Layer Errors 108
- Data Link Layer Errors 108
- Transaction Layer Errors 109
- Error Type Description 110
- Status Bit Conditions 112
- IP Core Architecture 114
- Hard IP for PCI Express 115
- Top-Level Interfaces 116
- Avalon-MM DMA Interface 116
- Clocks and Reset 116
- Transceiver Reconfiguration 116
- Interrupts 116
- Data Link Layer 117
- Physical Layer 119
- TX Packets 120
- Altera FPGA 122
- Qsys System 123
- Subscribe 125
- Address[31:2] 130
- Figure A-6: I/O Read Request 132
- Additional Information 136
- Date Version Changes Made 137
- How to Contact Altera 139
- Typographic Conventions 140
- Visual Cue Meaning 141
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