Altera V-Series Avalon-MM DMA Manual do Utilizador descarregar pdf (Página 102)

Reset Sequence for Hard IP for PCI Express IP Core and Application Layer

Figure 6-2: Hard IP for PCI Express and Application Logic Reset Sequence

Your Application Layer can instantiate a module similar to the one in this figure to generate app_rstn,

which resets the Application Layer logic.

pin_perst

pld_clk_inuse

serdes_pll_locked

crst

32 cycles

srst

reset_status

app_rstn

This reset sequence includes the following steps:

1. After pin_perst or npor is released, the Hard IP reset controller waits for pld_clk_inuse to be

asserted.

2. csrt and srst are released 32 cycles after pld_clk_inuse is asserted.

3. The Hard IP for PCI Express deasserts the reset_status output to the Application Layer.

4. The altpcied_<device>v_hwtcl.sv deasserts app_rstn 32 pld_clkcycles after reset_status is released.

UG-01154

2014.12.18

Reset Sequence for Hard IP for PCI Express IP Core and Application Layer

6-3

Reset and Clocks

Altera Corporation

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Altera V-Series Avalon-MM DMA Manual do Utilizador Página 102