Altera V-Series Avalon-MM DMA Manual do Utilizador Página 16
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plan to replace the Descriptor Controller IP core with your own implementation, do not turn on the
Instantiate internal descriptor controller in the parameter editor when parameterizing the IP core.
Transceiver Reconfiguration Controller IP Core
The Transceiver Reconfiguration Controller performs offset cancellation to compensate for variations due
to process, voltage, and temperature (PVT).
The following provides a high-level block diagram of the V-Series Avalon-MM DMA for PCI Express
Design Example.
Altera PCIe Reconfig Driver IP Core
The PCIe Reconfig Driver drives the Transceiver Reconfiguration Controller. This driver is a plain text
Verilog HDL file that you can modify if necessary to meet your system requirements.
Block Diagram of the Avalon-MM DMA for PCI Express Example Design
Transaction,
Data Link,
and PHY
Layers
On-Chip
Memory
DMA Data
Descriptor
Controller
Qsys System Design V-Series Avalon-MM DMA for PCI Express
PCIe Link
Gen3 x8
DMA Engine
Avalon-MM to
PCIe TLP
Bridge
V-Series Avalon-MM DMA for PCI Express
Altera PCIe
Reconfig
Driver
Transceiver
Reconfiguration
Controller
Interconnect
Related Information
• V-Series Avalon-MM DMA for PCI Express on page 8-8
• DMA Descriptor Controller Registers on page 5-15
Generating the Testbench
1. Copy the example design, pcie_de_ep_dma_g3x8_integrated.qsys, from the installation directory:
<install_dir>/ip/altera/altera_pcie/altera_pcie_hip_256_avmm/example_design/ to your working directory.
2. Start Qsys, by typing the following command:
2-2
Generating the Testbench
UG-01154
2014.12.18
Altera Corporation
Getting Started with the Avalon-MM DMA
Send Feedback
- User Guide 1
- Features 3
- Interface 5
- Release Information 8
- Example Designs 9
- Debug Features 9
- IP Core Verification 9
- Related Information 10
- Altera Corporation 11
- Datasheet 11
- Send Feedback 11
- Parameter Value 17
- Directory Description 18
- Time TLP Type Payload 18
- TLP Header 18
- Creating a Quartus II Project 19
- Compiling the Design 20
- Parameter Settings 22
- Parameter Value Description 23
- Device Capabilities 28
- Error Reporting 28
- Link Capabilities 29
- MSI and MSI-X Capabilities 29
- Power Management 30
- PCIe Address Space Settings 31
- RX Master Module 36
- TX Slave Module 38
- Signal Name Directio 39
- Description 39
- Bits Name Description 41
- Clock Signals 45
- Signal Direction Description 46
- MSI Interrupts for Endpoints 51
- Serial Data Signals 53
- 9 Ch 18 Ch 54
- PIPE Interface Signals 64
- Test Signals 68
- Registers 70
- Altera-Defined VSEC Registers 77
- CvP Registers 78
- Bits Register Description 82
- Register Access Description 86
- Read DMA Example 91
- Byte Offset 95
- Register Dir Description 95
- Reset and Clocks 100
- Example Design 101
- Hard IP for PCI Express 101
- UG-01154 102
- 2014.12.18 102
- Clock Domains 104
- Data Rate Frequency 105
- Clock Summary 106
- Error Handling 107
- Physical Layer Errors 108
- Data Link Layer Errors 108
- Transaction Layer Errors 109
- Error Type Description 110
- Status Bit Conditions 112
- IP Core Architecture 114
- Hard IP for PCI Express 115
- Top-Level Interfaces 116
- Avalon-MM DMA Interface 116
- Clocks and Reset 116
- Transceiver Reconfiguration 116
- Interrupts 116
- Data Link Layer 117
- Physical Layer 119
- TX Packets 120
- Altera FPGA 122
- Qsys System 123
- Subscribe 125
- Address[31:2] 130
- Figure A-6: I/O Read Request 132
- Additional Information 136
- Date Version Changes Made 137
- How to Contact Altera 139
- Typographic Conventions 140
- Visual Cue Meaning 141
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