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Altera Corporation User Guide Version 11.1 3–15

October 2011

Functional Description

Parameterized Configuration Register Signals

Table 3–3 summarizes the PCI local interface signals for the

parameterized configuration register signals.

Table 3–4 shows definitions for the command register output bus bits.

Table 3–3. Parameterized Configuration Register Signals

Name Type Polarity Description

cache[7..0]

Output –

Cache line-size register output. The

cache[7..0] bus is

the same as the configuration space cache line-size register.

The local-side logic uses this signal to provide support for

cache commands.

cmd_reg[6..0]

Output –

Command register output. The

cmd_reg[6..0] bus drives

the important signals of the configuration space command

stat_reg[6..0]

Output –

Status register output. The

stat_reg[6..0] bus drives

the important signals of the configuration space status

Table 3–4. PCI Command Register Output Bus (cmd_reg[6..0]) Bit Definition

Bit Number Bit Name Description

io_ena

I/O accesses enable. Bit 0 of the command register.

mem_ema

Memory access enable. Bit 1 of the command register.

mstr_ena

Master enable. Bit 2 of the command register. This signal is

reserved for

pci_t64 and pci_t32.

mwi_ena

Memory write and invalidate enable. Bit 4 of the command register.

perr_ena

Parity error response enable. Command register bit 6.

serr_ena

System error response enable. Command register bit 8.

int_dis (1)

Interrupt disable. Command register bit 10.

Note to Ta ble 3 –4 :

(1) This signal is added for compliance with the PCI Local Bus Specification, Revision 3.0.

1 2 ... 84 85 86 87 88 89 90 91 92 93 94 ... 359 360

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