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Altera Corporation User Guide Version 11.1 8–1

October 2011

8. Testbench

General

Description

The Altera PCI testbench facilitates the design and verification of systems

that implement the Altera PCI-Avalon bridge. The testbench is provided

in both VHDL and Verilog HDL. When you build your system with the

PCI-Avalon bridge, SOPC Builder automatically integrates the PCI

testbench with your system testbench files.

SOPC Builder creates the pci_sim directory in your project directory and

copies all the PCI testbench files from <path>/pci_compiler/

sopc_flow/testbench/<language>/<core> into

<project directory>/pci_sim.

1 The testbench files must be edited to add the PCI transactions

that will be performed on the system. If you regenerate your

system, SOPC Builder will not overwrite the testbench files in

the pci_sim directory. If you want the default testbench files,

first delete the pci_sim directory and then regenerate your

system.

Figure 8–1 shows the block diagram of the PCI testbench. The shaded

blocks are provided with the PCI testbench.

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