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Altera Corporation User Guide Version 11.1 4–7

October 2011 PCI Compiler

Testbench

Table 4–5 shows the testbench's target termination support. The master

transactor and the local master respond to the target terminations by

terminating the transaction gracefully and releasing the PCI bus.

Master Transactor (mstr_tranx)

The master transactor simulates the master behavior on the PCI bus. It

serves as an initiator of PCI transactions for Altera PCI testbench. The

master transactor has three main sections:

■ PROCEDURES (VHDL) or TASKS (Verilog HDL)

■ INITIALIZATION

■ USER COMMANDS

PROCEDURES and TASKS Sections

The PROCEDURES (VHDL) and TASKS (Verilog HDL) sections define

the events that are executed for the user commands supported by the

master transactor. The events written in the PROCEDURES and TASKS

sections follow the phases of a standard PCI transaction as defined by the

PCI Local Bus Specification, Revision 3.0, including:

■ Address phase

■ Turn-around phase (read transactions)

■ Data phases

■ Turn-around phase

The master transactor terminates the PCI transactions in the following

cases:

■ The PCI transaction has successfully transferred all the intended data

■ The PCI target terminates the transaction prematurely with a target

retry, disconnect, or abort as defined in the PCI Local Bus Specification,

Revision 3.0

■ A target does not claim the transaction resulting in a master abort

Table 4–5. PCI Testbench Target Termination Support

Features Master Transactor Target Transactor Local Master Local Target

Target abort

Target retry

vvvv

Target disconnect

vvvv

1 2 ... 212 213 214 215 216 217 218 219 220 221 222 ... 359 360

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