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7–20 User Guide Version 11.1 Altera Corporation

PCI Compiler October 2011

PCI Target Operation

A PCI read operation handled by the non-prefetchable bridge data path

has the following sequence of events:

1. In the request phase, the PCI bus issues a read transactions that

matches one of the BARs. The PCI-Avalon bridge claims the

transaction, stores its address, command and byte enables, and

issues a retry. The PCI-Avalon bridge claims transactions only if

there are no other transactions pending in the non-prefetchable data

path.

2. The PCI-Avalon bridge translates the PCI address to Avalon-MM

and passes the transaction to the non-prefetchable Avalon-MM

master port, which issues the transaction to the interconnect.

3. The data retrieved from Avalon is stored in a read response register

inside the PCI-Avalon bridge. The PCI-Avalon bridge will then wait

for the PCI bus to issue the same read transaction.

4. Finally, during the completion phase, the PCI bus issues the same

read transaction with exactly the same address, command and byte

enables, and then the PCI-Avalon bridge transfers the data, which

signals the end of the non-prefetchable read operation.

While the PCI-Avalon is processing the non-prefetchable read, all

transactions are retried and not remembered.

Due to the required ordering rules, if there is a pending write transaction

in the opposite direction (Avalon-to-PCI), the non-prefetchable read

operation’s completion phase will be delayed. In other words, if a write

operation (flowing in the opposite direction of the current read operation)

is in the Avalon bridge first, the PCI-Avalon bridge will not complete the

read operation until the write operation completes.

If the non-prefetchable read latency timer expires before the read

transaction is complete, the non-prefetchable read transaction’s data is

discarded. The non-prefetchable read latency counter is set to 32,768

clocks.

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Altera PCI Compiler Manual do Utilizador Página 288