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Altera Corporation User Guide Version 11.1 15
October 2011
About PCI Compiler
Table 9 lists memory utilization and performance data for Cyclone II
devices.
Table 10 lists memory utilization and performance data for Stratix,
Stratix GX, and Cyclone devices.
Table 9. Memory Utilization & Performance Data for Cyclone II Devices (2)
PCI
Device
Mode
Performance Setting as: (1) 32-Bit PCI Interface 64-Bit PCI Interface
PCI
f
MAX
(MHz)
PCI Target PCI Master
Logic
Elements
(LEs)
M4K
Memory
Blocks
I/O
Pins
Logic
Elements
(LEs)
M4K
Memory
Blocks
I/O
Pins
PCI
Target-
Only
Min N/A 547 0 48 1,114 0 87 >67
Typical N/A 1,113 4 48 1,565 6 87 >67
Max N/A 1,605 4 48 2,051 6 87 >67
PCI
Master/
Target
Min Typical 2,117 7 50 3,075 9 89 >67
Typical Typical 2,319 9 50 3,391 13 89 >67
Max Typical 2,806 9 50 3,915 13 89 >67
Min Max 3,096 7 50 4,655 9 89 >67
Typical Max 3,328 9 50 4,939 13 89 >67
Max Max 3,806 9 50 5,454 13 89 >67
Notes to Ta b le 9 :
(1) Min = Single-cycle transactions
Typical = Burst transactions with a single pending read
Max = Burst transactions with multiple pending reads
(2) The data was obtained by performing compilations on a Cyclone II EP2C35F672C7 device. Each of the device types
was parameterized to use one BAR that reserved 1 MByte of memory on the Avalon-MM side. For the PCI
Master/Target Peripheral mode, one MByte of memory was reserved on the PCI side.
Table 10. Memory Utilization & Performance Data for Stratix, Stratix GX & Cyclone Devices (3) (Part 1
of 2)
PCI
Device
Mode
Performance Setting as: (1) 32-Bit PCI Interface 64-Bit PCI Interface
PCI
f
MAX
(MHz)
PCI Target PCI Master
Logic
Elements
(LEs)
M512
Memory
Blocks
(2)
I/O
Pins
Logic
Elements
(LEs)
M512
Memory
Blocks
(2)
I/O
Pins
PCI
Target-
Only
Min N/A 852 0 48 1,186 0 87 >67
Typical N/A 1,460 4 48 1,949 6 87 >67
Max N/A 1,940 4 48 2,442 6 87 >67
- PCI Compiler 1
- User Guide 1
- UG-PCICOMPILER-4.12 3
- Chapter 2. Parameter Settings 6
- Chapter 4. Testbench 7
- Chapter 5. Getting Started 8
- Chapter 6. Parameter Settings 8
- Chapter 8. Testbench 10
- Additional Information 11
- Contents 12
- About PCI Compiler 13
- Release 14
- Information 14
- Device Family 14
- Features 15
- General 17
- Description 17
- PCI Testbench 18
- General Description 20
- Selecting the 21
- Appropriate 21
- Flow for Your 21
- Compliance 22
- Performance 23
- Utilization 23
- Installation and 29
- Licensing 29
- <path> 30
- OpenCore Plus Evaluation 31
- Installation and Licensing 32
- Section I. PCI Compiler 33
- With MegaWizard Plug-In 33
- Manager Flow 33
- 1. Getting Started 35
- PCI MegaCore 36
- Function Design 36
- Launch IP Toolbench 38
- Step 1: Parameterize 39
- Step 2: Set Up Simulation 41
- Step 3: Generate 41
- The Quartus II 46
- Simulation Files 46
- Master Simulation Files 47
- Target Simulation Files 49
- PCI Timing 52
- Using the 53
- Reference 53
- Designs 53
- Using the Reference Designs 58
- 2. Parameter Settings 59
- Advanced PCI 61
- MegaCore 61
- Function 61
- Master Features 62
- Variation File 65
- Parameters 65
- HARDWIRE_BARn 67
- HARDWIRE_EXP_ROM 67
- MAX_64_BAR_RW_BITS 68
- NUMBER_OF_BARS 68
- ENABLE_BITS 68
- INTERRUPT_PIN_REG 69
- PCI_66MHZ_CAPABLE 69
- HARDWIRE_BARn_ENA 69
- HARDWIRE_EXP_ROM_ENA 69
- EXP_ROM_ENA 69
- CAP_LIST_ENA 70
- CIS_PTR_ENA 70
- INTERRUPT_ACK_ENA 70
- INTERNAL_ARBITER_ENA (1) 70
- MW_CBEN_ENA 73
- Variation File Parameters 74
- 3. Functional Description 75
- PCI Bus Signals 85
- "). The signals lm_ackn 93
- Target Local-Side Signals 94
- Master Local-Side Signals 98
- PCI Bus 101
- Commands 101
- Configuration 102
- Registers 102
- Vendor ID Register 105
- Device ID Register 105
- Command Register 106
- Status Register 107
- Revision ID Register 108
- Class Code Register 109
- Cache Line Size Register 109
- Latency Timer Register 110
- Header Type Register 110
- Base Address Registers 111
- Reserved 113
- CardBus CIS Pointer Register 114
- Subsystem Vendor ID Register 114
- Subsystem ID Register 115
- Capabilities Pointer 116
- Interrupt Line Register 116
- Interrupt Pin Register 117
- Minimum Grant Register 117
- Target Mode 118
- Operation 118
- October 2011 119
- Functional Description 119
- Target Read Transactions 122
- PCI Compiler October 2011 124
- Target Mode Operation 124
- Note Figure 3–7: 124
- Clock Cycle Event 125
- Note to Figure 3–8: 128
- Note to Figure 3–9: 129
- Note to Figure 3–10: 130
- Note to Figure 3–12: 134
- I/O Read Transactions 135
- Target Write Transactions 137
- Note to Figure 3–15: 138
- Note to Figure 3–16: 142
- Note to Figure 3–17: 143
- Note to Figure 3–18: 144
- Note to Figure 3–19: 146
- Note to Figure 3–20: 148
- I/O Write Transactions 149
- Note to Figure 3–23: 152
- Disconnect 153
- Note to Figure 3–24: 154
- Note to Figure 3–25: 155
- Note to Figure 3–26: 156
- Note to Figure 3–27: 157
- Target Abort 160
- Note to Figure 3–30: 161
- Master Mode 162
- Master Mode Operation 164
- PCI Bus Parking 166
- Master Read Transactions 167
- Notes to Figure 3–31: 169
- Note to Figure 3–32: 173
- Notes to Figure 3–33: 174
- Notes to Figure 3–34: 176
- Notes to Figure 3–35: 178
- Note to Figure 3–36: 179
- Master Write Transactions 182
- Notes to Figure 3–38: 184
- Note to Figure 3–39: 188
- Notes to Figure 3–40: 189
- Notes to Figure 3–41: 191
- Notes to Figure 3–42: 193
- Note to Figure 3–43: 194
- Latency Timer Expires 199
- Disconnect Without Data 200
- Disconnect with Data 200
- Master Abort 200
- Host Bridge 201
- Host Bridge Operation 202
- Note to Figure 3–46: 202
- Note to Figure 3–47: 204
- Addressing 205
- Dual Address 205
- Cycle (DAC) 205
- 4. Testbench 211
- File(1) Description 213
- Testbench 216
- Specifications 216
- PROCEDURES and TASKS Sections 217
- Refer to the 218
- INITIALIZATION Section 218
- USER COMMANDS Section 218
- FILE IO section 223
- PROCEDURES and TASKS sections 223
- Bus Monitor (monitor) 224
- Clock Generator (clk_gen) 224
- Local Reference 225
- Description 226
- Local Target 227
- DMA Engine 227
- Local Master 229
- Prefetch 229
- LPM RAM 229
- Simulation Flow 230
- October 2011 PCI Compiler 231
- Section II. PCI Compiler 233
- With SOPC Builder Flow 233
- 5. Getting Started 235
- Builder Flow 236
- Walkthrough 236
- Set Up the PCI-Avalon Bridge 239
- Getting Started 241
- Simulate the 245
- Compile the 247
- Program a 248
- Upgrading 249
- Systems from a 249
- Previous 249
- Program a Device 250
- 6. Parameter Settings 251
- System Options-1 252
- PCI Target Performance 253
- PCI Master Performance 255
- Value of 256
- Multiple 256
- Pending Reads 256
- Interconnect 257
- Options-2 259
- PCI Bus Arbiter 260
- Parameter Settings 263
- PCI Configuration 264
- 0 . . . 0 265
- 0 AV BASE 265
- X X X X X . . . X 265
- Avalon Configuration 268
- 7. Functional Description 269
- PCI-Avalon Bridge Blocks 270
- Avalon-MM Ports 271
- PCI MegaCore Function 273
- PCI Operational Modes 274
- Functional Overview 276
- ■ PCI Host-Bridge Device mode 277
- Performance Profiles 279
- Target Performance 280
- Master Performance 280
- Interface 281
- PCI Bus Arbiter Signals 282
- PCI Target 283
- Non-Prefetchable Operations 285
- I/O Write Operations 287
- PCI Target Operation 288
- Prefetchable Operations 289
- Prefetchable Write Operations 290
- Prefetchable Read Operations 291
- PCI Master 295
- Avalon-to-PCI Write Requests 299
- Avalon-to-PCI Read Requests 300
- PCI Master Operation 304
- Ordering of Requests 306
- ■ DRC—Delayed read completion 307
- PCI Host-Bridge 313
- Altera-Provided 313
- Interrupts 314
- Control & Status 315
- PCI Interrupt Status Register 317
- PCI Interrupt Enable Register 319
- PCI Mailbox Register Access 320
- “Avalon 322
- Configuration” on page 6–16 322
- Bit Name 326
- MASTER_ENABLE_CURRENT_VALUE 327
- A2P_WRITE_IN_PROGRESS 327
- INTAN_CURRENT_VALUE 327
- CraIrq_o) to be asserted 328
- 8. Testbench 331
- BAR0 x10 342
- Arbiter (arbiter) 344
- Pull Up (pull_up) 344
- Appendix A. Using PCI 347
- Constraint File Tcl Scripts 347
- Simultaneous 348
- Switching Noise 348
- Considerations 348
- Additional 349
- -no_compile 353
- -no_pinouts 353
- -pin_prefix 353
- -pin_suffix 353
- Assignments 354
- Version of PCI 354
- Compiler 354
- How to Contact 358
- Typographic 359
- Conventions 359
- Typographic Conventions 360
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