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8–4 User Guide Version 11.1 Altera Corporation

PCI Compiler October 2011

Testbench Specifications

Refer to “Simulation Flow” on page 8–15 for more information on the

modified testbench files.

Testbench

Specifications

This section describes the modules used by the PCI testbench including

master commands, setting and controlling target termination responses,

bus parking, and PCI bus speed settings. Refer to Figure 8–1 for a block

diagram of the PCI testbench. The Altera PCI testbench has the following

modules:

■ Master transactor (mstr_tranx)

■ Target transactor (trgt_tranx)

■ Bus monitor (monitor)

■ Clock generator (clk_gen)

■ Arbiter (arbiter)

■ Pull ups (pull_ups)

■ A local reference design

The PCI testbench consists of VHDL and Verilog HDL. If your application

requires a feature that is not supported by the PCI testbench, you can

modify the source code to add the feature. You can also modify the

existing behavior to fit your application needs.

Table 8–2 shows the PCI bus transactions supported by the PCI testbench.

pci_tb This top-level file instantiates all the testbench

modules.

Note to Ta b le 8 – 1:

(1) All files are provided in both VHDL and Verilog HDL.

Table 8–1. Files Contained in the pci_sim/<HDL language>/<core>

Directory (Part 2 of 2)

File(1) Description

Table 8–2. PCI Testbench PCI Bus Transaction Support (Part 1 of 2)

Transactions Master Transactor Target Transactor Local Master Local Target

Interrupt acknowledge cycle

I/O read

vvvv

I/O write

vvvv

Memory read

vvvv

Memory write

vvvv

Configuration read

1 2 ... 329 330 331 332 333 334 335 336 337 338 339 ... 359 360

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