Altera Shift Register IP Core Manual do Utilizador descarregar pdf

LPM_SHIFTREG Megafunction

2013.03.05

UG-033105

Feedback

This document describes the Altera

-provided megafunction IP core optimized for Altera

device

architectures. Using megafunctions instead of coding your own logic saves valuable design time, offering

more efficient logic synthesis and device implementation. Scale the megafunction's size by simply setting

parameters.

Features

The LPM_SHIFTREG megafunction implements a shift register and offers many additional features, including:

• Synchronous or asynchronous inputs to shift register

• Synchronous parallel load

• Left/right register shifting

• Optional inputs, including clock enable input, serial shift data input, and parallel input

• Optional outputs, including data output and serial shift data output

General Description

The LPM_SHIFTREG megafunction is a memory compilation IP core accessible from the Quartus II

MegaWizard

Plug-In Manager.

Shift registers are a type of sequential logic circuit, that mainly store digital data. These cores are comprised

of a group of flip-flops connected in a chain so that the output from one flip-flop becomes the input of the

next flip-flop. All the flip-flops are driven by a common clock and are set or reset simultaneously. A shift

no characteristic internal sequence of states.

The shift register megafunction is highly parameterizable block of logic. You can use this megafunction to

implement long delay chains. The megafunction provides for either left shift or right shift of the input data

bits. Shifted data is either loaded in parallel into the registers synchronously, or in serial through the shiftin

input of the megafunction. The loaded data is then shifted with the rising edge of clock input.

The shift operation is a single clock-edge operation with an active-high clock enable feature. When enable

is High, the input (D) is loaded into the first bit of the shift register, and each bit is shifted to the next highest

bit position. Cascading of shift registers is another way of using the LPM_SHIFTREG megafunction to

achieve higher shift count or bit count.

Optional inputs are available to asynchronously clear or set the registers, or synchronously clear or set the

registers. Using this feature, you can either set the initial value of all the registers to 1, or to a desired value.

Parallel output q[] is used to read parallel data from the shift register. Parallel data is always available on

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Resumo do Conteúdo

Página 1 - LPM_SHIFTREG Megafunction

LPM_SHIFTREG Megafunction2013.03.05UG-033105SubscribeFeedbackThis document describes the Altera®-provided megafunction IP core optimized for Altera®de

Página 2 - Device Family Support

The support page has links to topics such as installation, usage, and troubleshooting.Set up the ModelSim-Altera simulator by performing the following

Página 3 - Resource Utilization

10. Under What outputs do you want (select at least one)?, turn off the Data output option and turn onthe Serial shift data output option.11. Under Do

Página 4 - Altera Corporation

Ports and ParametersThe options listed in this section describe all of the ports and parameters available for each device to customizethe LPM_SHIFTREG

Página 5 - DescriptionFunction

CommentsDescriptionRequiredPort NameSets q[] outputs to value specified by LPM_SVALUE, if that value is present, or sets the qoutputs to all 1s. If bo

Página 6

CommentsRequiredTypeParameterConstant value loaded when aset is high. If omitted,defaults to all 1s. The LPM_AVALUE parameter islimited to a maximum o

Página 7

the q[] outputs at every clock. When data is shifted serially with every clock, you get the MSB of the q[]output on theq[] pin.Common ApplicationsUse

Página 8 - Simulating Megafunctions

SupportDevice FamilyFullStratixPreliminaryCyclone®V (E, GX, GT, SE, SX)FullCyclone IV (E and GX)FullCyclone IIIFullCyclone IIFullCyclonePreliminaryArr

Página 9

• In the Quartus II software, click Tools > MegaWizard Plug-In Manager.• In the Project Navigator, right-click a megafunction file and click MegaWi

Página 10 - Design Example: Time Delay

Related InformationCreating a System with QsysParameters in the MegaWizard Plug-In Manager GUIThe LPM_SHIFTREG wizard guides you through the process o

Página 11 - Feedback

DescriptionFunctionSome files are automatially selected by the MegaWizard Plug-In Manager.The choices are:• Variation file, (<function name>.v/.

Página 12 - Ports and Parameters

LPM_SHIFTREG AHDL Function PrototypeThe following AHDL function prototype is located in the AHDL Include File (.inc) lpm_shiftreg.inc in the<Quartu

Página 13 - CommentsRequiredTypeParameter

Simulating MegafunctionsSimulation verifies design behavior before device programming. The Quartus II software supports RTL andgate level design simul

Página 14 - Revision History

Generating a Configurable 8-Bit SIPO or PISO Shift RegisterTo build and configure the LPM_SHIFTREG megafunction with the configurable 8-bit SIPO or PI

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