Altera Triple Speed Ethernet MegaCore Function Manual do Utilizador Página 171

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9
Timing Constraints
2014.06.30
UG-01008
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Altera provides timing constraint files (.sdc) to ensure that the Triple-Speed Ethernet MegaCore function
meets the design timing requirements in Altera devices. The files constraints the false paths and multi-cycle
paths in the Triple-Speed Ethernet Megacore function. The timing constraints files are specified in the
<variation_name>.qip file and is automatically included in the Quartus II project files.
You may need to add timing constraints that are external to the MegaCore function. The following sections
describe the procedure to create the timing constraint file.
Creating Clock Constraints
After you generate and integrate the Triple-Speed Ethernet MegaCore function into the system, you need
to create a timing constraints file to specify the clock constraint requirement.
You can specify the clock requirement in the timing constraint file using the following command:
create_clock
For example, for a new clock named "reg_clk", with a 50 MHz clock targeted to the top level input port
"clk", enter the following command line:
create_clock -name "reg_clk" -period "50 MHz" [get_ports "clk"]
Figure 91 shows an example of how you can create a timing constraint file to constrain the Triple-Speed
Ethernet MegaCore function clocks.
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