Altera Triple Speed Ethernet MegaCore Function Manual do Utilizador descarregar pdf (Página 166)

Figure 8-2: Clock Distribution in MAC and 1000BASE-X PCS with GXB Configuration—Optimal Case

Figure shows the optimal clock distribution scheme you can achieve in configurations that contain the

10/100/1000 Ethernet MAC, 1000Base-X PCS, and GX transceivers.

ALTGX

(GIGE Mode )

ALTGX

(GIGE Mode )

ALTGX

(GIGE Mode )

Quad

Transceivers

ALTGX

(GIGE Mode )

Port 2

4-port MAC

ca l_blk_c lk

ref _ clk

tbi _ rx _clk 1

tbi _ rx _clk 2

tbi _ rx _clk 3

tbi _ rx _clk 4

rx _ clk 1

tx _ clk 1

rx _clk 2

tx _ clk 2

rx _ clk 3

tx _ clk 3

To s ubs e que n t Q u a ds, if a ny

Port 4

Port 3

rx _ clk 4

tx _ clk 4

clk 1

clk 2

clk 3

clk 4

PCS 1

PCS 2

PCS 3

PCS 4

tbi _ tx _ clk

Port 1

Note to Figure 8–2 :

1. The PMA layer in devices with GX transceivers uses ALTGX megafunctions.

MAC and PCS With LVDS Soft-CDR I/O

In configurations that contain the MAC, PCS, and LVDS Soft-CDR I/O, you have the following options in

optimizing clock resources:

• Utilize the same reset signal for all MAC instances if you do not require a separate reset for each instance.

• Utilize the same clock source to drive the reference clock, FIFO transmit and receive clocks, and system

clocks, if these clocks run at the same frequency.

Design Considerations

Altera Corporation

Send Feedback

UG-01008

MAC and PCS With LVDS Soft-CDR I/O

8-4

2014.06.30

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