Altera Triple Speed Ethernet MegaCore Function Manual do Utilizador descarregar pdf (Página 133)

Arria 10 Transceiver Native PHY Signals

Table 7-22: Arria 10 Transceiver Native PHY Signals

DescriptionI/OName

Serial clock input from the transceiver PLL. The frequency of this clock

depends on the data rate and clock division factor.

Itx_serial_clk

Reference clock input to the receive clock data recovery (CDR)

circuitry.

Irx_cdr_refclk

Resets the analog transmit portion of the transceiver PHY.Itx_analogreset

Resets the digital transmit portion of the transceiver PHY.Itx_digitalreset

Resets the analog receive portion of the transceiver PHY.Irx_analogreset

Resets the digital receive portion of the transceiver PHY.Irx_digitalreset

When asserted, this signal indicates that the transmit channel is being

calibrated.

Otx_cal_busy

When asserted, this signal indicates that the receive channel is being

calibrated.

Orx_cal_busy

Force the receiver CDR to lock to the incoming data.Irx_set_locktodata

Force the receiver CDR to lock to the phase and frequency of the input

reference clock.

Irx_set_locktoref

When asserted, this signal indicates that the CDR PLL is locked to the

incoming data rx_serial_data.

Orx_is_lockedtodata

When asserted, this signal indicates that the CDR PLL is locked to the

incoming reference clock, rx_cdr_refclk.

Orx_is_lockedtoref

Related Information

Arria 10 Transceiver PHY User Guide

More information about Gigabit Ethernet (GbE) and GbE with 1588, the connection guidelines for a PHY

design, and how to implement GbE/GbE with 1588 in Arria 10 Transceivers

Interface Signals

Altera Corporation

Send Feedback

UG-01008

Arria 10 Transceiver Native PHY Signals

7-18

2014.06.30

1 2 ... 128 129 130 131 132 133 134 135 136 137 138 ... 222 223

Sem comentários

Altera Triple Speed Ethernet MegaCore Function Manual do Utilizador Página 133