Altera POS-PHY Level 4 IP Core Manual do Utilizador Página 78
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5–8 Chapter 5: Functional Description—Transmitter
Clock Structure
POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation
Figure 5–3 on page 5–8 gives an example of the timing for the status bypass port.
Clock Structure
With the Atlantic FIFO clock mode parameter in IP Toolbench, you can parameterize
the transmitter in one of the following two clocking structures:
■ Single clock domain
■ Multiple clock domain
All data path width variations of the IP core use a common clocking structure.
1 All clocks are asynchronous and paths between the domains can be cut.
The transmitter has three primary clock domains.
The first primary clock domain is associated with the SPI-4.2 transmit status channel
and is controlled by the
tsclk
input. All of the logic pertaining to the SPI-4.2 status
channel processing is controlled by this clock.
The second primary clock domain is a a common clock,
tdint_clk
, which the IP core’s
protocol logic and all Atlantic FIFO buffers share. This
tdint_clk
clocks both the
write and read sides of the Atlantic FIFO buffers. The
tdint_clk
is an output of the IP
core, and is derived from
trefclk
via the phase-locked loop (PLL) in the transmit
altlvds
block.
The third primary clock domain relays received transmit status channel information
to the user logic. This clock domain is controlled by the
txsys_clk
signal. In most
applications,
txsys_clk
is on the same domain as
tdint_clk
, but they are separated
for flexibility.
Single Clock Domain
In the single clock domain mode, the Atlantic FIFO buffers are instantiated as single
clock domain buffers, thereby consuming fewer logic resources.
Figure 5–3. Example Timing Diagram for the Status Bypass Port
tsclk
stat_ts_sync
stat_ts_disabled
stat_ts_dip2state
stat_ts_frmstate
stat_ts_extstat_adr
stat_ts_extstat
33000033000
03
2'b00 2'b00 2'b00 2'b01 2'b02 2'b03 2'b00 2'b00 2'b00 2'b01 2'b02 2'b03 2'b00
- User Guide 1
- POS-PHY Level 4 IP Core 1
- 1. About This IP Core 3
- General Description 5
- Interfaces & Protocols 6
- IP Core Verification 7
- OpenCore Plus IP Evaluation 9
- 2. Getting Started 11
- Using the Parameter Editor 12
- Upgrading Outdated IP Cores 13
- Specify Parameters 15
- Simulate the Design 17
- 3. Parameter Settings 21
- LVDS Data Rate 22
- PLL Input Frequency 23
- Data Path Width 23
- Buffer Mode 23
- Basic Parameters 24
- Atlantic FIFO Buffer Clock 25
- Atlantic Interface Width 25
- Optional Features 26
- Transmitter Options 27
- Receiver Options 28
- Starving Starving Starving 29
- Starving Hungry Hungry 29
- Starving Satisfied Satisfied 29
- FIFO RAM Blocks 30
- Note to Table 3–5: 31
- Protocol Parameters 32
- Features 39
- Block Description 39
- ALTLVDS_RX IP Core 41
- Data Processor (rx_data_proc) 42
- Atlantic Buffers 43
- Individual Buffers 44
- Status Processor 45
- Notes to Figure 4–3: 46
- Note to Table 4–1: 47
- Notes to Figure 4–4: 48
- Requirements for rxsys_clk 49
- Reset Structure 50
- Error Flagging and Handling 50
- SPI-4.2 Protocol Errors 51
- Notes to Table 4–3: 53
- DIP-4 Marking 54
- Notes to Figure 4–8: 56
- Missing SOP 59
- Missing EOP 60
- Note to Table 4–7: 62
- Note to Table 4–8: 63
- Note to Table 4–9: 63
- Latency Information 68
- Data Processor (tx_data_proc) 74
- Status Bypass Port 77
- Clock Structure 78
- Multiple Clock Domain 79
- Notes to Figure 5–4: 80
- Note to Table 5–5: 88
- 6. Testbench 99
- Variation 100
- Receiver 100
- Receiver Testbench Examples 101
- 6–4 Chapter 6: Testbench 102
- Chapter 6: Testbench 6–5 103
- 6–6 Chapter 6: Testbench 104
- Chapter 6: Testbench 6–7 105
- 6–8 Chapter 6: Testbench 106
- A. Start-Up Sequence 107
- Troubleshooting 109
- Issues and Tips—Miscellaneous 111
- Separate PLLs 113
- Shared PLL 113
- "<rx_pll>" 114
- Note to Table C–1: 115
- D. Board Design 117
- Probe Points 118
- Spare Pins 119
- JTAG Scan Chain 119
- D–4 Appendix D: Board Design 120
- Design for Testability 120
- Introduction 121
- Static Alignment 125
- Dynamic Alignment 126
- Altera Solutions 126
- Dynamic Phase Alignment (DPA) 127
- AC Timing Analysis 128
- Budgets 129
- G. Conversion from v2.2.x 131
- Receiver Signals 132
- Transmitter Signals 134
- Additional Information 139
- Note to Table: 140
- Additional Information Info–3 141
- Typographic Conventions 141
- Info–4 Additional Information 142
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