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Appendix A: Start-Up Sequence A–3

Troubleshooting

December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide

Troubleshooting

This section provides some troubleshooting issues and tips.

Issues and Tips—Transmitter

Transmitter tips:

1. The PLL locked signal is not asserted or toggles. Ensure that the input clock jitter is

within the PLL jitter requirements. In some cases, if the PLL locked signal toggles

the PLL must be reset. If so, perform the appropriate steps listed in Table A–1 on

page A–2. Refer to your PLL’s documentation for further information.

2. Status channel does not sync. This problem can occur when

stat_ts_sync

remains

low, and/or

stat_ts_disabled

toggles or remains high and/or

err_ts_frm

and/or

err_ts_dip2

toggles. The following tips may prove useful:

■ For 128-bit receiver variations, ensure that the

rxsys_clk

rdint_clk

ratio is

set according to the receive clock setting in Table C–1 on page C–1.

■ Ensure that the calendar length and calendar multiplier are set to the same

values in both devices.

■ Verify timing requirements for the status channel.

■ Select the clock edge that drives or samples the clock with

ctl_ts_statedge

and

ctl_rs_statedge

■ Verify t

for the

rsclk

and

rstat

pins in the receiver IP core. The ALTDDIO IP

core keeps on-chip skew to a minimum.

■ Verify board skew for

rsclk

rstat

■ Verify the setup and hold times for

tstat

tsclk

in the transmit IP core. The

ALTDDIO IP core keeps on-chip skew to a minimum.

■ Verify that

tsclk

is operating at the correct frequency.

Issues and Tips—Receiver

Receiver tips:

Trained —Non-DPA

variations of

receiver IP cores

A single training pattern is required to obtain

lock.

—

6Ready

The data path is deskewed and error signals

are valid.

stat_rd_rdat_sync

is asserted

once the Atlantic buffers are ready and the

DIP-4 out-of-service clears. The receiver is

ready to receive data and transmits valid

status frames.

Device correctly receives a

good_level

(

ctl_ts_sync_good_threshold

) of status

frames and asserts

stat_ts_sync

The transmitter is ready to transmit data. It

transmits idles or data.

Table A–1. Start-Up Sequence (Part 2 of 2)

Event Description Receiver IP Core Transmitter IP Core

1 2 ... 104 105 106 107 108 109 110 111 112 113 114 ... 141 142

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