Altera POS-PHY Level 4 IP Core Manual do Utilizador Página 24
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3–4 Chapter 3: Parameter Settings
Basic Parameters
POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation
For transmitters for individual buffers variations, a credit-based scheduler is
provided. This scheduler decodes the incoming status channel and decides from
which FIFO buffer (port) to transmit.
The individual buffers for transmitters offer the following advantages:
■ A simple user interface
■ Full scheduler
■ No head-of-line blocking
■ Per-port backpressure
f For further information on individual buffers for transmitters, refer to “Individual
Buffers” on page 5–3.
For receivers, the individual buffers offer the following advantages:
■ A simple user interface
■ No head-of-line blocking
■ The POS-PHY Level 4 IP core handles all of the backpressure automatically
f For further information on individual buffers for receivers, refer to “Individual
Buffers” on page 4–6.
The SPI-4.2 protocol supports from 1 to 256 ports. When you select the number of
ports, you determine the mode of operation. Single-PHY operation for one port; or
multi-PHY for two to 256 ports. For example, when interfacing to a 10-channel Gbit
Ethernet MAC device the number of ports is 10.
When you use the shared buffer with embedded addressing, the Number of ports
determines the number of port addresses supported by the POS-PHY Level 4 protocol
portion of the IP core, such as the status generator and error checker. Port addresses 0
to 255 can always be sent and received when using Shared buffer with embedded
addressing.
For the shared buffer with embedded addressing, the Buffer size defines the size of
the shared embedded address buffer. For the individual buffers, the Buffer size
defines the size of each buffer. The POS-PHY Level 4 IP core supports the following
sizes (per buffer):
■ 512 bytes
■ 1,024 bytes
■ 2,048 bytes
■ 4,096 bytes
■ 8,192 bytes
■ 16,384 bytes
■ 32,768 bytes
- User Guide 1
- POS-PHY Level 4 IP Core 1
- 1. About This IP Core 3
- General Description 5
- Interfaces & Protocols 6
- IP Core Verification 7
- OpenCore Plus IP Evaluation 9
- 2. Getting Started 11
- Using the Parameter Editor 12
- Upgrading Outdated IP Cores 13
- Specify Parameters 15
- Simulate the Design 17
- 3. Parameter Settings 21
- LVDS Data Rate 22
- PLL Input Frequency 23
- Data Path Width 23
- Buffer Mode 23
- Basic Parameters 24
- Atlantic FIFO Buffer Clock 25
- Atlantic Interface Width 25
- Optional Features 26
- Transmitter Options 27
- Receiver Options 28
- Starving Starving Starving 29
- Starving Hungry Hungry 29
- Starving Satisfied Satisfied 29
- FIFO RAM Blocks 30
- Note to Table 3–5: 31
- Protocol Parameters 32
- Features 39
- Block Description 39
- ALTLVDS_RX IP Core 41
- Data Processor (rx_data_proc) 42
- Atlantic Buffers 43
- Individual Buffers 44
- Status Processor 45
- Notes to Figure 4–3: 46
- Note to Table 4–1: 47
- Notes to Figure 4–4: 48
- Requirements for rxsys_clk 49
- Reset Structure 50
- Error Flagging and Handling 50
- SPI-4.2 Protocol Errors 51
- Notes to Table 4–3: 53
- DIP-4 Marking 54
- Notes to Figure 4–8: 56
- Missing SOP 59
- Missing EOP 60
- Note to Table 4–7: 62
- Note to Table 4–8: 63
- Note to Table 4–9: 63
- Latency Information 68
- Data Processor (tx_data_proc) 74
- Status Bypass Port 77
- Clock Structure 78
- Multiple Clock Domain 79
- Notes to Figure 5–4: 80
- Note to Table 5–5: 88
- 6. Testbench 99
- Variation 100
- Receiver 100
- Receiver Testbench Examples 101
- 6–4 Chapter 6: Testbench 102
- Chapter 6: Testbench 6–5 103
- 6–6 Chapter 6: Testbench 104
- Chapter 6: Testbench 6–7 105
- 6–8 Chapter 6: Testbench 106
- A. Start-Up Sequence 107
- Troubleshooting 109
- Issues and Tips—Miscellaneous 111
- Separate PLLs 113
- Shared PLL 113
- "<rx_pll>" 114
- Note to Table C–1: 115
- D. Board Design 117
- Probe Points 118
- Spare Pins 119
- JTAG Scan Chain 119
- D–4 Appendix D: Board Design 120
- Design for Testability 120
- Introduction 121
- Static Alignment 125
- Dynamic Alignment 126
- Altera Solutions 126
- Dynamic Phase Alignment (DPA) 127
- AC Timing Analysis 128
- Budgets 129
- G. Conversion from v2.2.x 131
- Receiver Signals 132
- Transmitter Signals 134
- Additional Information 139
- Note to Table: 140
- Additional Information Info–3 141
- Typographic Conventions 141
- Info–4 Additional Information 142
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