Altera POS-PHY Level 4 IP Core Manual do Utilizador descarregar pdf (Página 43)

Chapter 4: Functional Description—Receiver 4–5

Block Description

December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide

■ SOP8 violations. If SOPs occur less than 8 cycles apart, the

err_rd_sop8

signal is

asserted but there is no impact on the received data. In 128- and 64-bit variations,

the clock-domain crossing buffer may fill faster when SOP8 violations occur.

■ Odd size packet violations. If an odd size packet does not end with the LSB cleared

to zero, the

aN_arxerr

signal is asserted on EOP. The

err_rd_pad_byte_non_zero

signal is also asserted.

■ EOP aborts. If an EOP abort is received, the

aN_arxerr

signal is asserted on EOP.

The

err_rd_eop_abort

signal is also asserted.

■ DIP-4 errors (refer to “DIP-4 Marking” on page 4–16 and “DIP-4 Out of Service

Indication” on page 4–17).

■ Reserved control words—data is dropped.

■ Proper training patterns. The channel aligner block requires proper training

patterns to lock, so if the transmitting device is sending bad training patterns, the

err_rd_tp

signal is asserted and the IP core does not lock.

1 Whenever the IP core aborts a packet by asserting the

aN_arxerr

signal (as

in the odd size packet with LSB not cleared), the resulting packet is even

sized, except in the DIP-4 optimistic mode.

f For a more complete list of errors detected by the IP core, refer to “Error Flagging and

Handling” on page 4–12.

Clock-Domain Crossing Buffer

This block instantiates a clock-domain crossing buffer called alignment buffer (ABUF)

to transfer data from the

rdint_clk

clock domain to the

rxsys_clk

clock domain. The

depth of the alignment buffer is fixed at 128; the width is equal to the IP core data path

width.

f For a description of the relationship between

rdint_clk

and

rxsys_clk

, refer to

“Clock Structure” on page 4–9.

SOP Alignment & Atlantic Conversion

This block moves the SOP for each packet to the first-byte position on the Atlantic

interface, and aligns the data to ensure that valid data is contiguous (no IDLEs) before

sending it to the Atlantic buffer.

Atlantic Buffers

The Atlantic FIFO buffers provide the following features:

■ Single receive slave-source Atlantic interface on the user end

■ Configurable buffer size

■ Support for crossing clock domains

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