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Chapter 5: Functional Description—Transmitter 5–7
Block Description
December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide
When the ignore backpressure feature is turned off (always off for the individual
buffers mode), and the status channel informs the Atlantic converter that one port is
satisfied, all ports stop sending.
Status Channel Interpretation Modes
The status FIFO buffers of the transmitter IP core support two status channel
interpretation modes: pessimistic and optimistic. The mode is applied to the status
sent to the scheduler (individual buffers mode) and to the user logic.
Pessimistic Mode
The last calendar length of the incoming status frame is stored in a FIFO buffer until a
DIP-2 is received. If a DIP-2 containing errors is received, the status from that frame is
dropped, and the transmit scheduler does not get any new credits. If the DIP-2 is
errorless, the status is sent to the user logic and scheduler.
1 The pessimistic mode causes the latency in receiving a valid status message to be
calendar multiplier × calendar length
tsclk
cycles longer than the optimistic mode. This
is significant for systems with large calendar length or large calendar multiplier
values.
Optimistic Mode
The status information is provided to the user and transmit scheduler as soon as it can
pass through the clock-crossing FIFO buffers, before the DIP-2 cycle is even received.
DIP-2 errors are flagged, but have no effect on the status provided to the user, or to the
scheduler.
1 In either mode, the
stat_ts_dip2state
signal indicates when a DIP-2 has been
received at the finite state machine.
Status Bypass Port
The status bypass port copies the values of the status signals going to the IP core. DIP-
2 errors are not calculated on this port. The port is output only and can therefore be
left unconnected or undeclared. This interface provides the following signals on the
tsclk
:
■
stat_ts_sync
■
stat_ts_disabled
■
stat_ts_dip2state
■
stat_ts_frmstate
■
stat_ts_extstat_adr
■
stat_ts_extstat
f For more information on the signals, refer to Table 5–7 on page 5–19.
- User Guide 1
- POS-PHY Level 4 IP Core 1
- 1. About This IP Core 3
- General Description 5
- Interfaces & Protocols 6
- IP Core Verification 7
- OpenCore Plus IP Evaluation 9
- 2. Getting Started 11
- Using the Parameter Editor 12
- Upgrading Outdated IP Cores 13
- Specify Parameters 15
- Simulate the Design 17
- 3. Parameter Settings 21
- LVDS Data Rate 22
- PLL Input Frequency 23
- Data Path Width 23
- Buffer Mode 23
- Basic Parameters 24
- Atlantic FIFO Buffer Clock 25
- Atlantic Interface Width 25
- Optional Features 26
- Transmitter Options 27
- Receiver Options 28
- Starving Starving Starving 29
- Starving Hungry Hungry 29
- Starving Satisfied Satisfied 29
- FIFO RAM Blocks 30
- Note to Table 3–5: 31
- Protocol Parameters 32
- Features 39
- Block Description 39
- ALTLVDS_RX IP Core 41
- Data Processor (rx_data_proc) 42
- Atlantic Buffers 43
- Individual Buffers 44
- Status Processor 45
- Notes to Figure 4–3: 46
- Note to Table 4–1: 47
- Notes to Figure 4–4: 48
- Requirements for rxsys_clk 49
- Reset Structure 50
- Error Flagging and Handling 50
- SPI-4.2 Protocol Errors 51
- Notes to Table 4–3: 53
- DIP-4 Marking 54
- Notes to Figure 4–8: 56
- Missing SOP 59
- Missing EOP 60
- Note to Table 4–7: 62
- Note to Table 4–8: 63
- Note to Table 4–9: 63
- Latency Information 68
- Data Processor (tx_data_proc) 74
- Status Bypass Port 77
- Clock Structure 78
- Multiple Clock Domain 79
- Notes to Figure 5–4: 80
- Note to Table 5–5: 88
- 6. Testbench 99
- Variation 100
- Receiver 100
- Receiver Testbench Examples 101
- 6–4 Chapter 6: Testbench 102
- Chapter 6: Testbench 6–5 103
- 6–6 Chapter 6: Testbench 104
- Chapter 6: Testbench 6–7 105
- 6–8 Chapter 6: Testbench 106
- A. Start-Up Sequence 107
- Troubleshooting 109
- Issues and Tips—Miscellaneous 111
- Separate PLLs 113
- Shared PLL 113
- "<rx_pll>" 114
- Note to Table C–1: 115
- D. Board Design 117
- Probe Points 118
- Spare Pins 119
- JTAG Scan Chain 119
- D–4 Appendix D: Board Design 120
- Design for Testability 120
- Introduction 121
- Static Alignment 125
- Dynamic Alignment 126
- Altera Solutions 126
- Dynamic Phase Alignment (DPA) 127
- AC Timing Analysis 128
- Budgets 129
- G. Conversion from v2.2.x 131
- Receiver Signals 132
- Transmitter Signals 134
- Additional Information 139
- Note to Table: 140
- Additional Information Info–3 141
- Typographic Conventions 141
- Info–4 Additional Information 142
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